Firestorm: FCCMPE (scalar, D) measurements

Code:

  fccmpe d0, d1, #0, lt

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	2037	15	0	61	937	25	1000	1000	1000	68984	0	2018	2084	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	12	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	61	937	25	1000	1000	1000	68984	1	2054	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2085	2038	2038
1004	2037	15	3	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	1	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038

Test 2: Latency 3->1

Chain cycles: 2

Code:

  fccmpe d0, d1, #0, lt
  fcsel d0, d2, d3, eq

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	300	2	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	0	1310	2	26	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	156	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	11	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	1	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	251	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	0	1310	1	16	1	1	39909	8	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	0	0	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	1	3	0	0	1270	4	16	4	3	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	0	33	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	1270	4	17	4	5	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	1	0	0	0	0	103	39822	25	20010	10	20000	10	20000	50	2853880	0	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	1270	3	16	3	4	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	1270	4	16	4	3	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	1270	3	16	3	4	39910	0	10000	10	40038	40038	40038	40038	40085
20024	40037	300	0	1	0	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	1270	4	16	4	3	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	1	40018	40037	40037	37338	3	37517	20010	24	20000	20	61713	41228	40085	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	1270	3	16	3	4	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	1270	3	16	3	4	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	0	459	39822	25	20010	10	20000	10	20000	50	2853880	0	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	1270	4	16	3	3	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	301	0	0	0	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	1270	4	16	3	4	39910	0	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 3->2

Chain cycles: 2

Code:

  fccmpe d0, d1, #0, lt
  fcsel d1, d2, d3, eq

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	300	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	1310	0	0	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40084	300	0	0	1	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	1310	0	0	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	276	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	0	40018	40037	40037	37316	3	37495	20190	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	1310	0	0	1	16	1	1	39909	0	10000	100	40038	40038	40071	40038	40038
20204	40037	300	0	1	0	276	0	390	39822	25	20100	100	20000	100	20000	500	2853880	0	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40179	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	1310	0	0	2	26	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	1310	0	0	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	102	0	61	39822	25	20122	100	20000	100	20000	500	2853880	1	0	40018	40037	40037	37316	3	37495	20100	200	20091	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	1310	0	0	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	1310	0	0	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	0	0	61	39822	25	20118	106	20000	100	20000	500	2854371	0	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	1310	0	0	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60291	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	1310	0	0	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	0	40018	40037	40037	37316	3	37522	20100	200	20097	200	60000	40037	40037	2	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	1310	0	0	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	299	0	2	0	0	0	291	0	726	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	726	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20372	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	3	1286	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	12	0	61	39822	25	20010	10	20000	10	20080	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	916	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	0	1270	1	16	1	2	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20091	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 3->3

Code:

  fccmpe d0, d1, #0, lt

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	536	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	710	0	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	71	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	9	0	0	710	0	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20228	150	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	710	0	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	985	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	3	0	710	0	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	1	3	0	712	0	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	120	0	712	0	3	16	4	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	346	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	2	3	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	1	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	2	1	10201	100	99	100	10000	10000	0	0	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	1	3	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	1	3	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	0	0	0	89	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	0	0	0	0	0	640	4	16	5	3	19969	10	10	20038	20038	20038	20038	20038
10024	20037	156	0	0	0	1	0	0	0	88	0	207	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	0	0	0	958	0	640	3	16	3	3	19969	10	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	0	382	9842	117	10080	24	10060	20	10220	107	707919	1	20198	20274	20276	18759	20	18928	10240	20	10286	20	31026	20271	20274	6	1	10021	10	9	10	10000	10000	4	2	2	0	1	0	4475	0	684	7	56	4	6	20157	10	10	20274	20275	20275	20276	20275
10024	20277	157	0	1	1	1	5	5	660	440	2	1207	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	21	18767	10020	20	10059	20	31044	20037	20367	7	1	10021	10	9	10	10000	10000	2	0	0	0	0	4	5538	0	640	4	16	3	3	19969	10	10	20274	20276	20038	20227	20275
10024	20274	157	0	0	1	0	5	5	936	616	0	2205	9785	152	10116	20	10084	22	10352	119	707880	0	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	2	0	0	1	0	0	0	640	4	16	4	3	19969	10	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	0	991	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	0	0	2	6	0	683	5	41	6	3	20077	10	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	0	89	9937	25	10034	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	0	0	0	0	0	688	6	41	4	6	20077	10	10	20132	20133	20179	20133	20132
10024	20130	161	0	1	1	1	3	3	408	264	0	575	9869	78	10056	20	10036	20	10044	108	707958	1	20126	20226	20224	18678	21	18896	10198	20	10115	20	30507	20225	20227	5	1	10021	10	9	10	10000	10000	2	2	2	1	0	4	3660	0	640	4	16	3	3	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	0	145	9937	25	10020	20	10000	20	10088	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	0	0	0	0	0	640	4	16	3	3	19969	10	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	0	82	9823	136	10082	20	10072	22	10264	130	707906	1	20198	20274	20319	18767	26	18958	10240	20	10338	20	31026	20317	20274	7	1	10021	10	9	10	10000	10000	0	0	0	0	1	0	0	0	640	3	16	3	4	19969	10	10	20038	20038	20038	20038	20038

Test 5: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  fccmpe d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmpe d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmpe d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmpe d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmpe d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmpe d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmpe d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmpe d0, d1, #0, lt

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
160204	80042	599	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	52	97	160100	80100	80000	80100	80000	400500	880000	0	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80079	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
160024	80042	599	0	0	0	0	0	0	0	297	25	160010	80010	80000	80010	80000	400050	880000	1	1	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	10022	3	1	1	36	17	2	1	1	9	8	80036	80000	15	11	10	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	0	0	0	57	25	160010	80010	80000	80050	80000	400050	880000	1	1	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	10022	3	1	1	6	17	2	1	1	10	9	80036	80000	15	11	10	80042	80042	80042	80042	80042
160024	80041	600	0	1	0	0	0	0	0	78	36	160010	80010	80000	80010	80000	400050	880000	1	1	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80077	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	10022	6	1	18	7	17	2	2	2	7	12	80036	80000	15	11	10	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	0	0	1	84	25	160010	80010	80000	80010	80000	400050	880000	0	1	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	9	10022	3	1	1	9	17	2	1	11	13	6	80036	80000	15	22	10	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	0	0	0	63	25	160010	80010	80000	80010	80000	400050	880000	0	1	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80092	80093	1	1	160021	10	9	10	80010	80000	80010	0	1	3	10070	6	2	1	7	17	2	1	9	12	6	80036	80000	15	22	10	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	144	352	0	57	25	160010	80010	80000	80010	80000	400050	880000	1	1	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	10022	3	1	1	8	17	2	1	9	15	14	80036	80000	15	11	10	80042	80042	80042	80042	80042
160024	80041	599	0	1	1	2	6	280	0	324	25	160010	80010	80000	80010	80000	400050	880000	1	1	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	10022	6	1	1	8	17	2	1	9	13	9	80036	80000	15	11	10	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	1	9	598	1	1135	25	160010	80010	80000	80010	80028	400050	880288	1	1	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	10022	3	1	1	10	17	2	1	9	12	6	80036	80000	15	11	10	80042	80042	80042	80042	80042
160024	80041	600	0	0	0	0	0	0	0	1815	25	160010	80010	80000	80010	80000	400050	880000	1	1	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	10022	3	1	1	9	17	2	1	9	6	7	80036	80000	30	22	10	80042	80042	80042	80042	80042
160024	80041	600	0	0	0	0	0	0	0	57	25	160010	80010	80000	80010	80000	400050	880000	1	1	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	10022	6	1	1	7	17	4	1	13	12	9	80036	80000	15	11	10	80042	80042	80042	80042	80042

FCCMPE (scalar, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations