Firestorm: FCCMPE (scalar, H) measurements

Code:

  fccmpe h0, h1, #0, lt

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	9f	l1d tlb access (a0)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	2037	16	0	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	2	16	2	2	1969	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	918	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	2	16	2	2	1969	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	2	16	2	2	1969	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	2	16	2	2	1969	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	3	16	3	3	1969	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	2	16	2	2	1969	2038	2038	2038	2038	2038
1004	2037	15	1	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	2	16	2	2	1969	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	2	16	2	2	1969	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	2	16	2	2	1969	2038	2038	2038	2038	2038
1004	2037	15	0	93	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	2	16	2	2	1969	2038	2038	2038	2038	2038

Test 2: Latency 3->1

Chain cycles: 2

Code:

  fccmpe h0, h1, #0, lt
  fcsel d0, d2, d3, eq

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	299	0	599	39822	25	20139	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	1310	1	16	1	1	39909	0	10000	100	40086	40038	40038	40038	40038
20204	40037	300	0	147	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	202	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	145	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	0	724	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	233	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40070	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	3	237	39822	44	20023	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	252	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	1	28	2	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	145	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	442	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	111	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	168	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	166	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 3->2

Chain cycles: 2

Code:

  fccmpe h0, h1, #0, lt
  fcsel d1, d2, d3, eq

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	299	0	0	0	0	0	0	0	126	39822	25	20116	100	20000	100	20080	565	2854371	40018	40037	40037	37316	3	37495	20100	200	20000	202	60288	40037	40084	1	1	20201	100	99	100	100	20000	20100	2	0	1	0	1068	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	1	0	1	0	0	0	0	210	39822	25	20100	100	20000	100	20000	500	2854371	40054	40037	40037	37316	3	37549	20182	200	20000	204	60000	40084	40037	3	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	1327	1	17	1	2	39979	9	10000	100	40085	40038	40084	40038	40038
20204	40037	300	0	0	0	0	0	0	0	82	39822	61	20100	116	20000	100	20000	500	2853880	40018	40133	40037	37316	3	37550	20277	200	20000	204	60546	40037	40084	1	1	20201	100	99	100	100	20000	20100	2	0	3	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40086	40038	40134	40086
20204	40132	300	0	0	0	0	609	0	2	4481	39822	61	20100	115	20000	100	20080	500	2853880	40054	40037	40084	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	2	0	3	0	1310	1	42	1	1	39909	0	10000	100	40085	40038	40085	40084	40038
20204	40037	300	0	0	0	0	12	0	0	169	39822	25	20100	111	20000	100	20000	500	2853880	40018	40131	40037	37316	11	37495	20100	200	20000	200	60000	40130	40037	3	1	20201	100	99	100	100	20000	20100	2	0	2	0	6	0	1352	1	33	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	1	0	2	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	40018	40037	40131	37341	3	37495	20273	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	2	1	0	3	2	1347	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	0	61	39822	61	20100	104	20000	100	20000	500	2853880	40018	40037	40037	37316	11	37495	20100	202	20191	200	60273	40037	40133	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	2283	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20205	40037	300	0	0	0	1	144	0	0	82	39822	43	20100	100	20012	118	20000	500	2853880	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40084	40037	3	1	20201	100	99	100	100	20000	20100	0	0	0	2	2288	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	92	0	726	39822	25	20100	100	20000	100	20000	500	2853880	40018	40037	40037	37316	3	37549	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40085
20204	40037	300	0	0	0	0	0	88	0	483	39822	25	20100	100	20000	120	20000	500	2853880	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	0	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	536	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	0	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	1	1	12	108	602	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	3	0	1270	1	16	0	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	82	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	0	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	0	0	61	39822	43	20010	10	20000	13	20000	50	2854862	1	40162	40037	40037	37359	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	2	0	2608	0	1270	1	16	0	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	3	0	1270	1	16	0	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	12	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	0	1	1	39910	10000	10	40038	40038	40038	40038	40069
20024	40037	300	0	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	0	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	0	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	15	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	1	0	0	1270	1	16	0	1	1	39910	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 3->3

Code:

  fccmpe h0, h1, #0, lt

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	0	710	0	4	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	0	710	0	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	0	710	0	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	27	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	2	0	0	0	0	0	0	710	0	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	1	710	0	4	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	149	0	0	0	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	55	0	6	0	0	710	1	3	16	3	4	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	330	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	0	710	1	3	16	3	4	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	285	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	15	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	640	3	16	2	2	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	1	0	0	640	2	16	2	2	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	24	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	640	2	16	2	2	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	82	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	640	2	16	2	2	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	640	2	16	2	2	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	640	2	16	2	2	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	640	2	16	2	2	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	640	2	16	3	2	19969	10	10	20038	20038	20038	20038	20038
10025	20037	150	0	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	640	2	16	2	2	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	640	2	16	2	2	19969	10	10	20038	20038	20038	20038	20038

Test 5: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  fccmpe h0, h1, #0, lt
  ands xzr, xzr, xzr
  fccmpe h0, h1, #0, lt
  ands xzr, xzr, xzr
  fccmpe h0, h1, #0, lt
  ands xzr, xzr, xzr
  fccmpe h0, h1, #0, lt
  ands xzr, xzr, xzr
  fccmpe h0, h1, #0, lt
  ands xzr, xzr, xzr
  fccmpe h0, h1, #0, lt
  ands xzr, xzr, xzr
  fccmpe h0, h1, #0, lt
  ands xzr, xzr, xzr
  fccmpe h0, h1, #0, lt

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
160204	80041	600	0	0	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	1	10110	6	16	1	1	80038	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	0	0	73	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	0	0	52	25	160100	80100	80000	80100	80000	400805	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	24	0	52	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	10110	1	16	1	1	80074	80000	100	80042	80079	80042	80042	80042
160204	80041	600	0	0	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	10110	1	16	2	1	80035	80000	100	80042	80042	80042	80042	80245
160204	80041	600	0	0	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	1	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
160024	80041	600	0	0	0	0	58	25	160010	80164	80000	80010	80000	400050	880000	1	1	80022	80041	80041	59979	3	60014	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	0	0	10022	3	1	1	4	16	2	1	1	3	4	80036	80000	20	14	10	80042	80042	80042	80042	80042
160024	80041	600	0	0	0	0	723	25	160010	80010	80000	80010	80000	400050	880000	1	1	80022	80041	80041	59979	3	60014	160137	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	0	0	10022	3	1	1	5	16	2	1	1	5	5	80036	80000	20	14	10	80042	80042	80042	80042	80042
160024	80041	600	0	0	0	0	58	25	160010	80010	80000	80010	80000	400050	880000	1	1	80022	80041	80041	59979	3	60014	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	0	0	10022	3	1	1	4	16	2	1	1	5	3	80036	80072	20	14	10	80042	80042	80042	80042	80042
160024	80041	599	0	0	18	0	58	25	160010	80010	80000	80010	80000	400050	880000	1	1	80022	80041	80041	59979	3	60014	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	0	0	10022	3	1	1	3	16	2	1	1	5	3	80036	80000	20	14	10	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	58	25	160010	80010	80000	80010	80000	400050	880000	1	1	80022	80041	80041	59979	3	60014	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	0	0	10052	3	1	1	5	16	2	1	1	5	5	80036	80000	20	29	10	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	58	25	160010	80010	80000	80010	80000	400050	880000	1	1	80022	80041	80041	59979	18	60014	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	0	0	10022	3	1	1	4	16	2	1	1	3	4	80036	80000	20	14	10	80042	80042	80042	80042	80042
160024	80041	600	0	0	0	0	64	25	160010	80010	80000	80010	80000	400050	880000	1	1	80022	80041	80041	59979	3	60014	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	0	0	10022	3	1	1	4	16	2	1	1	4	3	80036	80000	20	14	10	80042	80042	80042	80042	80042
160024	80041	600	0	4	0	0	58	25	160010	80010	80000	80010	80000	400050	880000	1	1	80022	80041	80041	59979	3	60014	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	0	0	10024	3	1	1	4	16	2	1	1	4	4	80036	80000	20	14	10	80042	80042	80080	80042	80042
160024	80041	599	0	0	0	0	438	25	160010	80010	80000	80010	80000	400050	880000	1	1	80022	80041	80041	59979	3	60014	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	0	0	10022	3	1	1	3	16	2	1	1	3	3	80036	80000	20	14	10	80042	80042	80042	80042	80042
160024	80041	600	0	0	0	0	142	25	160010	80010	80000	80010	80000	400050	880000	1	1	80022	80041	80041	59979	3	60014	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	0	0	10022	3	1	1	3	16	2	1	1	4	3	80036	80000	20	14	10	80042	80042	80042	80042	80042

FCCMPE (scalar, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations