Firestorm: FCCMP (scalar, D) measurements

Code:

  fccmp d0, d1, #0, lt

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	2037	16	0	0	61	937	25	1000	1000	1000	68984	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	937	25	1000	1000	1000	68984	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	937	25	1000	1000	1000	68984	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	1	0	61	937	25	1000	1000	1000	68984	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	108	61	937	25	1000	1000	1000	68984	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038

Test 2: Latency 3->1

Chain cycles: 2

Code:

  fccmp d0, d1, #0, lt
  fcsel d0, d2, d3, eq

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	299	0	0	717	0	61	39822	25	20100	100	20000	100	20000	500	2853880	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	3	0	0	0	0	1310	1	16	1	1	40054	0	10000	100	40038	40086	40086	40038	40038
20204	40037	299	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	3	0	0	1310	1	16	1	1	40051	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	30	88	103	39822	25	20100	100	20000	100	20000	500	2853880	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40228	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40135	40038	40038
20204	40037	300	0	0	39	0	61	39822	25	20100	100	20000	100	20000	500	2853880	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	69	0	61	39822	25	20100	100	20000	100	20000	500	2853880	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	60	0	61	39822	25	20100	100	20000	100	20000	500	2853880	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	54	0	61	39822	25	20100	100	20000	100	20000	500	2853880	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	12	0	82	39822	25	20100	100	20000	100	20000	500	2853880	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	2	3	0	0	0	0	1361	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	40018	40037	40037	37316	3	37495	20445	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40227	40038	40038
20204	40037	299	0	0	0	0	673	39822	25	20100	100	20000	100	20000	500	2853880	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	0	3	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40180	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	61	39822	25	20049	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	12	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40084	2	1	20021	10	9	10	10	20000	20010	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	21	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40085	40038
20024	40037	300	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	12	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	87	88	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	1270	1	16	2	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 3->2

Chain cycles: 2

Code:

  fccmp d0, d1, #0, lt
  fcsel d1, d2, d3, eq

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	300	0	61	39786	25	20100	100	20000	100	20000	500	2853880	40018	0	40037	40037	37323	6	37491	20100	200	20008	200	60024	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	1	1	1	1317	0	16	0	0	39919	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	156	39822	25	20100	100	20000	100	20000	500	2853880	40018	0	40037	40037	37323	6	37491	20100	200	20008	200	60024	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	1	1	1	1317	0	16	0	0	39919	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	40018	0	40037	40037	37323	6	37491	20100	200	20008	200	60024	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	1	1	1	1317	0	16	0	0	39919	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	40018	0	40037	40037	37323	6	37491	20100	200	20008	200	60024	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	1	1	1	1317	0	16	0	0	39919	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	61	39822	25	20100	100	20000	100	20000	500	2853880	40018	0	40037	40037	37323	6	37491	20100	200	20008	200	60024	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	1	1	1	1317	0	16	0	0	39919	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	61	39822	25	20100	100	20000	100	20000	500	2853880	40018	0	40037	40037	37323	6	37491	20100	200	20008	200	60024	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	1	1	1	1317	0	16	0	0	39919	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	726	39822	25	20100	100	20000	100	20000	500	2853880	40018	0	40037	40037	37323	6	37491	20100	200	20008	200	60024	40037	40037	1	1	20201	100	99	100	100	20000	20100	1	0	1	1	1	1317	0	16	0	0	39919	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	40018	0	40037	40037	37323	6	37491	20100	200	20008	200	60024	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	1	1	1	1317	0	16	0	0	39919	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	40018	0	40037	40037	37323	6	37491	20100	200	20008	200	60024	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	1	1	1	1317	0	16	0	0	39919	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	61	39822	25	20100	100	20000	100	20000	500	2853880	40018	0	40037	40037	37323	6	37491	20100	200	20008	200	60024	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	1	1	1	1317	0	16	0	0	39919	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	22	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	2	16	2	2	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20090	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	2	16	2	2	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	6	1270	2	16	2	2	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	2	16	2	2	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	2	16	3	2	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	1	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	2	16	2	2	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	2	16	2	3	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	2	16	2	2	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	2	16	2	2	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	1270	2	16	2	2	39910	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 3->3

Code:

  fccmp d0, d1, #0, lt

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	0	710	0	4	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	15	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	0	710	0	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	0	710	0	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	149	0	0	0	0	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	0	710	0	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	0	710	0	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	9	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	204	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	0	712	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	0	0	0	0	0	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	640	2	24	2	2	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	6	0	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	640	2	16	2	2	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	640	2	16	2	2	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	441	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	640	2	16	2	2	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	640	2	16	2	2	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	640	2	16	2	2	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	640	2	16	2	2	19969	10	10	20038	20038	20038	20038	20038
10024	20037	149	21	0	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	640	3	16	2	2	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	640	2	16	2	2	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	640	2	16	2	2	19969	10	10	20038	20038	20038	20038	20038

Test 5: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  fccmp d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmp d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmp d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmp d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmp d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmp d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmp d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmp d0, d1, #0, lt

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
160204	80041	599	0	0	0	0	705	25	160104	80104	80000	80107	80000	400529	880000	80022	80041	80041	59970	6	59993	160107	80208	80008	200	240024	80041	80041	1	1	160201	100	99	100	80100	80000	80100	71	0	0	1	1	1	10118	1	16	0	0	80038	80004	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	0	726	25	160104	80104	80000	80107	80000	400529	880000	80022	80041	80041	59970	6	59993	160107	80208	80008	200	240024	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	15	0	1	1	1	10118	0	16	0	0	80038	80004	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	0	2320	25	160100	80100	80000	80266	80000	400500	880000	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80245	80144	1	1	160201	100	99	100	80100	80000	80100	0	3	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	0	717	25	160100	80100	80000	80100	80000	400500	880000	80059	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	0	52	25	160100	80100	80000	80100	80111	400700	880000	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80092	80041	1	1	160201	100	99	100	80100	80000	80100	91	0	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	80022	80041	80041	59964	3	59999	160180	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	15	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	80022	80041	80041	59964	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	6	0	0	0	0	10110	1	16	1	1	80035	80000	100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
160024	80041	600	0	0	0	0	57	25	160010	80010	80000	80010	80000	400050	880000	0	1	0	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	10024	6	2	2	15	17	2	1	1	10	6	80036	80000	20	15	10	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	63	25	160010	80010	80000	80010	80000	400050	880000	0	1	0	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	10022	3	1	1	9	17	2	1	2	10	6	80036	80000	20	15	10	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	57	25	160010	80010	80000	80010	80000	400050	880000	1	1	0	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	10022	3	1	1	9	17	2	1	1	9	5	80036	80000	20	15	10	80042	80042	80042	80042	80042
160024	80041	600	0	0	0	0	762	25	160010	80010	80000	80010	80000	400050	880000	1	1	0	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	10022	3	1	1	10	17	2	2	1	7	11	80036	80000	40	30	10	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	722	25	160010	80010	80000	80010	80000	400050	880000	1	1	0	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	10022	3	1	1	7	17	2	1	1	7	10	80036	80000	20	15	10	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	57	25	160010	80010	80000	80010	80000	400050	880000	1	1	0	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240135	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	3	0	10022	3	1	1	6	17	2	1	1	6	11	80036	80000	20	15	10	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	57	25	160010	80010	80000	80010	80000	400050	880000	1	1	0	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	2	10022	3	1	1	7	17	4	2	2	6	10	80036	80000	20	15	10	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	57	25	160010	80010	80000	80010	80000	400050	880000	1	1	0	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	10022	3	1	1	6	17	2	1	1	7	11	80036	80000	20	15	10	80042	80042	80042	80042	80042
160024	80041	600	0	0	0	0	57	25	160010	80010	80000	80010	80000	400050	863990	1	1	0	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	10022	3	1	1	7	17	2	1	1	10	10	80036	80000	20	15	10	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	57	25	160010	80010	80000	80010	80000	400050	880000	1	1	0	80022	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	10022	3	1	1	11	17	2	1	1	6	11	80036	80000	20	15	10	80042	80042	80042	80042	80042

FCCMP (scalar, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations