Firestorm: FCCMP (scalar, H) measurements

Code:

  fccmp h0, h1, #0, lt

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	0	82	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	0	105	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	4	0	73	1	16	1	1	1969	2038	2038	2038	2038	2038

Test 2: Latency 3->1

Chain cycles: 2

Code:

  fccmp h0, h1, #0, lt
  fcsel d0, d2, d3, eq

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	300	0	0	0	0	87	0	907	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	3	4	0	0	1310	1	16	1	1	39941	14	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	6	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	726	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	1	2	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40086
20204	40037	299	0	0	0	0	0	0	726	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	1	0	0	1	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	299	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20022	10	9	10	10	20000	20010	0	0	0	9	1270	1	24	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40132	301	1	1	0	61	39822	25	20010	10	20000	13	20160	60	2853880	1	40018	0	40037	40037	37338	3	37517	20090	20	20000	20	60000	40085	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1303	1	32	1	1	39910	1	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	346	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	3	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	1	1	39952	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	536	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 3->2

Chain cycles: 2

Code:

  fccmp h0, h1, #0, lt
  fcsel d1, d2, d3, eq

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	300	12	0	103	39822	25	20100	100	20012	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	726	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	202	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	1	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	536	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	1310	1	16	1	1	39909	6	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	1310	1	16	1	1	39909	20	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	60000	40037	40037	1	1	20201	100	99	100	100	20000	20100	0	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	189	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	2	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	124	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	2	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	191	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	353	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	416	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	1	0	0	1270	1	16	1	2	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	241	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	1	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	469	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	237	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	274	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	60000	40037	40037	1	1	20021	10	9	10	10	20000	20010	0	0	0	0	1270	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 3->3

Code:

  fccmp h0, h1, #0, lt

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	inst simd alu (9a)	9f	ac	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	0	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	710	1	4	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	0	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	1	20018	0	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	0	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	0	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	3	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10205	20037	150	51	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	0	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	710	1	3	16	3	4	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	6	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	0	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	0	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	128	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	0	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	712	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	9937	25	10200	200	10000	200	10000	1100	707984	0	20018	0	20037	20037	18638	3	18745	10200	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	10000	10000	0	0	710	1	3	16	3	3	19969	100	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	61	9937	25	10020	20	10000	20	10000	110	707984	0	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	4	0	0	640	3	16	3	3	19969	10	10	20038	20038	20038	20038	20038
10024	20037	149	0	0	84	9937	25	10020	20	10000	20	10000	110	707984	1	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	1	0	0	640	3	16	3	3	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	232	9937	25	10020	20	10000	20	10000	110	707984	0	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	640	3	16	3	3	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9937	25	10020	20	10000	20	10000	110	707984	0	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	640	3	16	3	3	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9937	25	10020	20	10000	20	10000	110	707984	0	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	640	3	16	3	3	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	147	9937	25	10020	20	10000	20	10000	110	707984	0	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	640	3	16	3	3	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9937	25	10020	20	10000	20	10000	110	707984	0	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	640	3	16	3	3	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	1	0	61	9937	25	10020	20	10000	20	10000	110	707984	0	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	640	3	16	4	3	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9937	25	10020	20	10000	20	10000	110	707984	0	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	0	0	640	3	16	4	3	19969	10	10	20038	20038	20038	20038	20038
10024	20037	150	0	81	61	9937	25	10020	20	10000	20	10000	110	707984	0	20018	20037	20037	18660	3	18767	10020	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10000	10000	0	6	0	640	3	16	3	3	19969	10	10	20038	20038	20038	20038	20038

Test 5: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  fccmp h0, h1, #0, lt
  ands xzr, xzr, xzr
  fccmp h0, h1, #0, lt
  ands xzr, xzr, xzr
  fccmp h0, h1, #0, lt
  ands xzr, xzr, xzr
  fccmp h0, h1, #0, lt
  ands xzr, xzr, xzr
  fccmp h0, h1, #0, lt
  ands xzr, xzr, xzr
  fccmp h0, h1, #0, lt
  ands xzr, xzr, xzr
  fccmp h0, h1, #0, lt
  ands xzr, xzr, xzr
  fccmp h0, h1, #0, lt

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
160204	80041	599	0	0	0	0	0	0	1126	25	160100	80100	80000	80100	80000	400500	880000	80022	80041	80041	59964	0	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160202	100	99	100	80100	80000	80100	0	0	0	0	0	0	0	0	10110	0	3	16	4	3	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	0	0	0	2196	25	160100	80100	80000	80100	80000	400804	880000	80022	80041	80041	59964	0	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	0	0	0	10110	0	3	16	3	3	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	80022	80041	80041	59964	0	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	0	0	0	10110	0	3	16	4	4	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	0	0	0	2451	25	160100	80100	80000	80100	80000	400500	880000	80022	80041	80041	59964	0	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	0	0	0	10110	0	4	17	3	3	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	80022	80041	80041	59964	0	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	0	0	0	10110	0	3	16	3	3	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	80022	80041	80041	59964	0	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	0	0	0	10110	0	3	16	3	3	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	0	0	0	717	25	160100	80100	80000	80100	80000	400500	880000	80022	80041	80041	59964	0	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	0	0	0	10110	0	3	16	3	3	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	0	0	0	717	25	160100	80100	80000	80100	80000	400500	880000	80022	80041	80041	59964	0	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	0	0	0	10110	0	3	16	3	3	80035	80000	100	80042	80078	80042	80042	80042
160204	80041	599	0	0	0	0	0	0	717	25	160100	80100	80000	80100	80000	400500	880000	80022	80041	80041	59964	0	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	0	0	0	10110	0	3	16	3	3	80035	80000	100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	0	0	0	52	25	160100	80100	80000	80100	80000	400500	880000	80022	80041	80041	59964	0	3	59999	160100	80200	80000	200	240000	80041	80041	1	1	160201	100	99	100	80100	80000	80100	0	0	0	0	0	0	2	0	10110	0	3	16	3	3	80035	80000	100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
160024	80041	599	0	0	0	0	0	0	0	0	543	78	160010	80010	80000	80010	80000	400050	880000	1	1	0	80022	0	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80142	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	0	0	0	0	10024	8	1	1	9	17	4	1	1	13	11	80036	80000	20	30	10	80042	80042	80042	80042	80042
160024	80041	600	0	0	0	0	0	9	0	0	260	25	160010	80010	80000	80010	80000	400050	880000	1	1	5	80022	0	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	0	2126	0	0	10022	8	4	1	10	17	2	1	1	12	10	80036	80000	20	30	10	80042	80042	80042	80042	80042
160024	80041	600	0	0	0	0	0	0	0	0	189	25	160010	80010	80000	80010	80000	400050	880000	1	1	5	80022	0	80041	80041	60051	3	60020	160010	80020	80000	20	240000	80192	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	1	0	12	0	0	10022	8	4	1	10	17	2	1	1	12	10	80036	80000	20	15	10	80042	80042	80042	80093	80042
160024	80041	600	0	0	0	0	0	0	0	0	239	25	160010	80010	80000	80010	80000	400050	880000	1	1	5	80022	0	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	0	0	0	0	10022	8	4	1	11	17	2	1	1	10	13	80036	80000	20	15	10	80042	80042	80042	80042	80042
160024	80041	600	0	0	0	0	0	0	0	0	314	25	160010	80010	80000	80010	80000	400050	880000	1	1	5	80022	0	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	2	2	2	1	2	10055	2	0	10229	8	4	1	13	169	2	1	1	20	12	80827	80702	20	15	10	80753	81109	81009	81004	81060
160024	80955	607	3	1	2	16	19	2589	1584	0	3996	372	161174	80749	80480	80790	80550	402450	856431	1	1	5	80806	0	81060	81103	60279	62	60701	161297	80796	80693	20	242196	81054	80856	21	1	160021	10	9	10	80010	80000	80010	4	0	3	2	4	10235	0	0	10416	8	4	1	15	209	2	1	1	17	20	80792	80959	43	29	10	81310	80954	81307	81262	81363
160024	81001	609	1	0	0	18	26	3300	2200	1	4899	25	160010	80010	80000	80010	80000	400050	880000	1	1	5	80022	0	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	0	0	0	0	10022	8	4	1	14	17	2	1	1	12	13	80036	80000	20	15	10	80042	80042	80042	80042	80042
160024	80041	600	0	0	0	0	0	0	0	0	57	25	160010	80010	80000	80010	80000	400050	880000	1	1	5	80022	0	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	0	0	0	0	10022	8	4	1	12	17	2	1	1	14	13	80036	80000	20	15	10	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	0	9	0	0	829	25	160010	80010	80000	80010	80000	400050	880000	1	1	5	80022	0	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	0	0	0	0	10022	8	4	1	15	17	2	1	1	15	13	80036	80000	20	15	10	80042	80042	80042	80042	80042
160024	80041	600	0	0	0	0	0	0	0	0	212	25	160010	80010	80000	80010	80000	400050	880000	1	1	5	80022	0	80041	80041	59986	3	60020	160010	80020	80000	20	240000	80041	80041	1	1	160021	10	9	10	80010	80000	80010	0	0	0	0	0	0	0	0	10022	8	4	1	11	17	2	1	1	12	15	80036	80000	20	15	10	80042	80042	80042	80042	80042

FCCMP (scalar, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations