Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMEQ (scalar, D)

Test 1: uops

Code:

  fcmeq d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371590611687251000100010002646802018203720371572318951000100020002037203711100110000973116111787100020382038203820382038
100420371500611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371500611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371500611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371600611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371500611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371600611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371500611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371500611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  fcmeq d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371502316119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042008414908219687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100047101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371502706119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119989100001002003820038200382003820038
10204200371502226119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371502496119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000611968725100231110000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150021611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150033611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fcmeq d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000126351968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003721102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500021611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037151005153619687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371501006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100060670216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020065200372003718444318767100102010000202000020037200371110021109101010000104100640216221978510000102003820038200382003820038
10024200371501006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fcmeq d0, d8, d9
  fcmeq d1, d8, d9
  fcmeq d2, d8, d9
  fcmeq d3, d8, d9
  fcmeq d4, d8, d9
  fcmeq d5, d8, d9
  fcmeq d6, d8, d9
  fcmeq d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200591510211462580100100800001008000050064000002001920038200389973039996801002008000020016000020038200381180201100991001008000010000132511021611200350800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
80204200381500010525801001008000010080000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
802042003815000402580100100800001008000050064000002001920038200389973039996801002008000020016000020038200381180201100991001008000010000476511012611200350800001002003920039200392003920039
80204200911500014525801001008000010080000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019200382003899890399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
8020420038150004025801001008000010280000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100000511011621200350800001002003920039200392003920039
80204200381500314925801001008000010080000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100000511011612200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000005110116112003511800001002003920039200392003920090

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200471500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000050200516672003580000102003920039200392003920039
800242003815000063025800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000050200616552003580000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000250200516562003580000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000050200516752003580000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100040050200516552003580000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000050200716572003580000102003920039200392003920039
80024200381500033925800901080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000050200616562003580000102003920039200392003920039
800242003815000012325800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000050200716652003580000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000050200416762003580000102003920039200392003920087
80024200381490003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000050200516752003580000102003920039200392003920039