Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMEQ (scalar, S)

Test 1: uops

Code:

  fcmeq s0, s0, s1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715611687251000100010002646801201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
1004203715611687251000100010002646801201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
1004203715611687251000100010002646801201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
1004203715611687251000100010002646801201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
1004203715611687251000100010002646801201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
1004208415611687251000100010002646801201820372037157231895100010002000203720371110011000006073116111787100020382038203820382038
1004203716611687251000100010002646801201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
1004203715611687251000100010002646801201820372037157231895100010002000203720371110011000000673116111787100020382038203820382038
1004203715611687251000100010002646801201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
10042037151051687251000100010002646801201820372037157231895100010002000203720371110011000002073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  fcmeq s0, s0, s1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000006119687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000008219687251010010010000100100005002847680020018020037200371842291874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000053619687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197911100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715014519687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640316231978510000102003820038200382003820038
10024200371506119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000101000640216231978510000102003820038200382003820038
100242003715010319687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216231978510000102003820038200382003820038
100242003715082196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001050600640216221978510000102003820038200382003820038
100242003715036519687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216231978510000102003820038200382003820038
10024200371506119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216231978510000102003820038200382003820038
10024200371506119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640316221978510000102003820038200382003820038
100242003715026519687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216231978510000102003820038200382003820038
10024200371506119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371506119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216231978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fcmeq s0, s1, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l1i tlb fill (04)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371501010319687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102161119791100001002003820038200382003820038
1020420037150008219687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150008419687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500072619687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150008219687251011510010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500012419687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)091e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003714900906119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150001506119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010030640216221978510000102003820038200382003820038
1002420037150001807519687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150001206119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150003006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150001806119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371501027053619687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150001506119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fcmeq s0, s8, s9
  fcmeq s1, s8, s9
  fcmeq s2, s8, s9
  fcmeq s3, s8, s9
  fcmeq s4, s8, s9
  fcmeq s5, s8, s9
  fcmeq s6, s8, s9
  fcmeq s7, s8, s9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003815004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511031631200350800001002003920039200392003920039
802042003815004025801001168000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
8020420038150124025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200892003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150000039258001010800001080000506400001220019200382003899963100188001020800002016000020038200381180021109101080000100001000502001161120035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001120019200382003899963100188001020800002016000020038200381180021109101080000100000000502011161120035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001120019200382003899963100188001020800002016000020038200381180021109101080000100000000502011161120035080000102003920039200392003920039
800242003815000022239258001010800001080000506400001120019200382003899963100188001020800002016000020038200381180021109101080000100000000502011161120035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001120019200382003899963100188001020800002016000020038200381180021109101080000100000000502011161120035080000102003920039200392003920039
800242003815000022239258001010800001080000506400000120019200382003899963100188001020800002016000020038200381180021109101080000100000000502001161120035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001120019200382003899963100188001020800002016000020038200381180021109101080000100000000502011161120035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001120019200382003899963100188001020800002016000020038200381180021109101080000100000000502001161120035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001120019200382003899963100188001020800002016000020038200381180021109101080000100000000502011161120035080000102003920039200392003920039
800242003815000018939258001010800001080000506400001020019200382003899963100188001020800002016000020038200381180021109101080000100000000502001161120035080000102003920039200392003920039