Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMEQ (vector, 4S)

Test 1: uops

Code:

  fcmeq v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073316221787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
10042037150821687251000100010002646802018203720371572318951000100020002037203711100110001073216221787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
10042037160611687251000100010002646802018203720371572318951000100020002037203711100110000090216221787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110002073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  fcmeq v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150001471968725101001001000010010000500284768002001820037200371842961874110100200100082002001620037200371110201100991001001000010000001117180160019801100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842961874110100200100082002001620037200371110201100991001001000010000001117170160019802100001002003820038200382003820038
102042003714900611968725101001001000010010000500284768002001820037200371842971874010100200100082002001620037200371110201100991001001000010000001117180160019801100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842971874110100200100082002001620037200371110201100991001001000010000131117170160019802100001002003820038200382003820038
1020420037150002341968725101001001000010010000500284768002001820037200371842971874010100200100082002001620037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
102042003715100821968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
1020420037150302351968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000030007101161119791100001002003820038200852003820038
1020420037150914791967625101001001000011810600500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000030007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500189196872510010101000010100005028476802001820037200371844403187671001020100002020000200372003711100211091010100001010006403162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476802001820037200371844403187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
10024200371500103196872510010101000010100005028476802001820037200371844403187671001020100002020000200372003711100211091010100001003006402162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476802001820037200371844403187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
10024200371500135196872510010101000010100005028476802001820037200371844403187671001020100002020000200372003711100211091010100001010006402162219785010000102003820038200382003820038
1002420037150082196872510010101000010100005028476802001820037200371844403187671001020100002020000200372003711100211091010100001010006402162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476802001820037200371844403187671001020100002020000200372003711100211091010100001000106402162219785010000102003820038200382003820038
1002420037150082196872510010101000010100005028476802006520037200371844403187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476802001820037200371844403187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476802001820037200371844403187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fcmeq v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150061196872510100100100001001000050028476800020018200372003718422031874510100200100002002000020037200371110201100991001001000010000710011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800020018200372003718422031874510100200100002002000020037200371110201100991001001000010000710011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800020018200372003718422031874510100200100002002000020037200371110201100991001001000010000710011611197910100001002003820038200382003820038
1020420037150082196872510100100100001001000050028476800020018200372003718426031874510100200100002002000020037200371110201100991001001000010000710011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800020018200372003718422031874510100200100002002000020037200371110201100991001001000010000710011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800020018200372003718422031874510100200100002002000020037200371110201100991001001000010000710011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800020018200372003718422031874510100200100002002000020037200371110201100991001001000010010710011611197910100001002003820038200382003820038
10204200371500841968725101001001000010010000500284768000200182003720037184220318745101002001000020020000200372003711102011009910010010000100007100116111979126100001002003820038200382003820038
10204200371500425196872510100100100001001000050028476800020018200372003718422031874510100200100002002000020037200371110201100991001001000010000710011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800020018200372003718422031874510100200100002002000020037200371110201100991001001000010000710011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000015061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150000000685196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150000000688196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000006061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fcmeq v0.4s, v8.4s, v9.4s
  fcmeq v1.4s, v8.4s, v9.4s
  fcmeq v2.4s, v8.4s, v9.4s
  fcmeq v3.4s, v8.4s, v9.4s
  fcmeq v4.4s, v8.4s, v9.4s
  fcmeq v5.4s, v8.4s, v9.4s
  fcmeq v6.4s, v8.4s, v9.4s
  fcmeq v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003815000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511031622200350800001002003920039200392003920039
802042003815000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511021622200350800001002003920039200392003920039
802042003815000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511021622200350800001002003920039200392003920039
802042003815000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511021622200350800001002003920039200392003920039
802042003815000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511026622200350800001002003920039200392003920039
802042003815000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511021622200350800001002003920039200392003920039
802042003815000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511021622200350800001002003920039200392003920039
802042003815512213232525801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511021622200350800001002003920039200392003920039
802042003815000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511021622200350800001002003920039200392003920039
802042003815000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511031622200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420047150003925800101080000108000056640000020019020038200389996031001880010208000020160000200382003811800211091010800001005020116112003580000102003920039200392003920039
8002420038150103925800101080000108000050640000020019020038200389996031001880010208000020160000200382003811800211091010800001005020116112003580000102003920039200392003920039
80024200381500051425800101080000108000050640000020019020038200389996031001880010208000020160000200382003811800211091010800001005020116112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019020038200389996031001880010208000020160000200382003811800211091010800001005020116112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019020038200389996031001880010208000020160000200382003811800211091010800001005020116112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019020038200389996031001880010208000020160000200382003811800211091010800001005020116112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019020038200389996031001880010208000020160000200382003811800211091010800001005020116112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019020038200389996031001880010208000020160000200382003811800211091010800001005020116112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019020038200389996031001880010208000020160000200382003811800211091010800001035020116112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019020038200389996031001880010208000020160000200382003811800211091010800001005020116112003580000102003920039200392003920039