Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMGE (scalar, D)

Test 1: uops

Code:

  fcmge d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037161015088821687251000100010002646802018203720371572318951000100023282037208411100110002000073116111785100020382038203820382038
10042037160000611687441012100010002646802018203720371572318951000100020002037203711100110000000073216111830100020382074208520382086
10042037151112885721687251000100010002646802018203720371572318951000100020002037203711100110000000073216111787100020382038203820382038
1004203715000061168725100010001000264680201820372037157281895100010002000203720371110011000020038573216111787100020382038203820382038
10042037160000567168725100010001000264680201820372037157231895100010002000203720371110011000020053079116111787100020852121208620382085
1004208416001170611687251000100010002646802018203720371572318951000100020002037203711100110000302188573116111785100020382038203820382038
10042037160000611687251000100010002646802018203720371571318951000100020002037203711100110000000073116111787100020382038203820382038
10042037160000611687251000100010002646802054203720841572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371500601871687251000100010002646802018203720371571318951000100020002037203711100110000000073116111787100020382038203820382038
10042037150000611687251000100010002646802018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  fcmge d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010010071011611197910100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715006119643251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000710116111979119100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372008418422318745101002001000020020000200372003711102011009910010010000100063071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100021071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100063071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100072071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037153126119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100130640216221978510000102003820038200382003820038
10024200371611210319687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100100640216221978510000102003820038200382003820038
1002420037155126119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100100640216221978510000102003820038200382003820038
100242003715512152019687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037155035819687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037153087619687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820071200382003820038
10024200371530137919687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715306119687251001010100121010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100001640216221978510000102003820038200382003820038
1002420037153078619687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150090519687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100660640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fcmge d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000145196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196762510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001001007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000103196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500084196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371490189196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001003640216221978510000102003820038200382003820038
1002420037150061196762510010101000010101525028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316321978510000102003820038200382003820038
100242003715012147196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001003640216321978510000102003820038200382003820038
10024200371490124196872510010101000010100005028476800200182008620037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001020640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500156196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fcmge d0, d8, d9
  fcmge d1, d8, d9
  fcmge d2, d8, d9
  fcmge d3, d8, d9
  fcmge d4, d8, d9
  fcmge d5, d8, d9
  fcmge d6, d8, d9
  fcmge d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200491500000402580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000051103161120035800001002003920039200392003920039
80204200381500000452580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000012001902003820038997339996801002008000020016000020038200381180201100991001008000010000051101161220035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000012001902003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000012001902003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000012001902003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815000510402580100100800001008000050064000012001902003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500000004000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000000005020021643200350080000102003920039200392003920039
800242003815000000000003242580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000000005020021622200350080000102003920039200392003920039
80024200381500000000000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000000005020031622200350080000102003920039200392003920039
80024200381500000000000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000000005020041622200350080000102003920039200392003920039
80024200381500000000000392580090108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000000005020111622200350080000102003920039200392003920039
80024200381500000001000392580010108000010800005064000002001920038200389996310045800102080000201600002003820038118002110910108000010000000005020021622200350080000102003920039200392003920039
80024200381500000000000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000000005020021622200350080000102003920039200392003920039
80024200381500000000000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000000005020041644200350080000102003920039200392003920039
80024200381500000000000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000000005020021622200350080000102003920039200392003920039
80024200381500000000000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000000005020031632200350080000102003920039200392003920039