Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMGE (scalar, H)

Test 1: uops

Code:

  fcmge h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000373316111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110003073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002652042018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037160611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037160841687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  fcmge h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150008219687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010024100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715001214919687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371500010719687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371500022419687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371500010519687251010010010000106100005002847680020018201342003718422318745102652001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715001269119687621010010010000100100005002848963120018200372003718422318745102592001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000307101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500103196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640716661978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640716651978510000102003820038200382003820038
10024200371500726196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640716661978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640716551978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640716551978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640716761978510000102003820038200382003820038
10024200371500219196872510010101000010100005028476800200652003720037184443187671001020100002020000200372003711100211091010100001000640716551978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640616661978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640716671978510000102003820038200382003820038
1002420037150061196874510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640616771978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fcmge h0, h1, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000082196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000599196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020084200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002013420038200382003820038
1020420037150000124196872510100100100001001000050028476802001820037200371842231874510100200100002002032620037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100000710116111979111100001002003820038200382003820038
1020420037150000124196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071013411197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000069006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000018006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000012006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
10024200371500009006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
10024200371500009006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000093006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000027006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000015006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402163219853010000102003820038200382003820038
100242003715000024006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003716100000013019687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fcmge h0, h8, h9
  fcmge h1, h8, h9
  fcmge h2, h8, h9
  fcmge h3, h8, h9
  fcmge h4, h8, h9
  fcmge h5, h8, h9
  fcmge h6, h8, h9
  fcmge h7, h8, h9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051105161120035800001002003920039200392003920039
80204200381500013525801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101162120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500013525801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0309l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dbddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500000000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000000005020005160045200350080000102003920039200392003920039
80024200381500000000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000000005020006160055200350080000102003920039200392003920039
80024200381500000000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000000005020004160065200350080000102003920039200392003920039
80024200381500000000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001001000005020006160065200350080000102003920039200392003920039
8002420038150000000010922580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000000005020005160055200350080000102003920039200392003920039
80024200381500000000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000000005020406160055200350080000102003920039200392003920039
80024200381490000000392580010108000010800005064000011200192003820038999631001880010208000020160000200382003811800211091010800001000000005020006160065200350080000102003920039200392003920039
80024200381500000000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000000005020006160055200350080000102003920039200392003920039
80024200381500000000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000000005020004160045200350080000102003920039200392003920039
80024200381500000000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000000005020006160054200350080000102003920039200392003920039