Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMGE (scalar, zero, D)

Test 1: uops

Code:

  fcmge d0, d0, #0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203716006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371501686116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203716006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715036116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150126116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  fcmge d0, d0, #0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715011566119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000071021611197910100001002003820038200382003820038
10204200371500126119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100001071011611197910100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000371011611197910100001002003820038200382003820075
10204200371500188219686251010010010000100100005222847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500016619686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000054071011611197910100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000345611968625100101010000101000060284752112001820037200371844331876710010201000020100002003720037111002110910101000010006402162219854010000102003820038200382003820038
10024200371500038428701968625100101010000101000050284752102001820037200371844331876710012201000020100002003720037111002110910101000010006402162219786010000102003820038200382003820038
1002420037150000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010006402162619786010000102003820038200382003820038
10024200371500012611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010306402162219786010000102003820038200382003820038
100242003715000288611968625100101010000101000050284752102001820037200371844331876710012201000020100002003720037111002110910101000010006402162219786010000102003820038200382003820038
1002420037150000611968625100101010000101000050284752102001820037200371844331876710012201000020100002003720037111002110910101000010006402162219786010000102003820038200382003820038
10024200371500084611968625100121210000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010006402162219786010000102003820038200382003820038
10024200371500003461968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010006402162219786010000102003820038200382003820038
1002420037150000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010006402162219786010000102003820038200382003820038
1002420037150000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010006402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  fcmge d0, d8, #0
  fcmge d1, d8, #0
  fcmge d2, d8, #0
  fcmge d3, d8, #0
  fcmge d4, d8, #0
  fcmge d5, d8, #0
  fcmge d6, d8, #0
  fcmge d7, d8, #0
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042004815003272925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000011151181620035800001002003920039200392003920039
80204200381500692925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000011151181620035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000011151181620035800001002003920039200392003920039
802042003815004592925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000011151181620035800001002003920039200392003920039
802042003815003872925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000011151181620035800001002003920039200392003920039
802042003815003332925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000011151181620035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000011151181620035800001002003920039200392003920039
8020420038150002925801801008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000011151181620035800001002003920039200392003920039
802042003815003902925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000011151181620035800001002003920039200392003920039
802042003815004292925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000011151181620035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915000136724403925800101080095108048950643852020179020293202861003831004580498208047920804862034120284618002110910108000010202000005020216112003580000102003920039200392003920039
8002420038150000090392580010108000010800005064000002001902003820038999631001880010208000020800002003820038118002110910108000010000000005020116112003580000102003920039200392003920039
80024200381500000002272580010108000010800005064000002001902003820038999631001880010208000020800002003820038118002110910108000010000000005037116112003580000102003920039200392003920039
8002420038150000000392580010108000010800005064000002001902003820038999631001880010208000020800002003820038118002110910108000010003000005020116112003580000102003920039200392003920039
8002420038150000000392580010108000010800005064000002001902003820038999631001880010208000020800002003820038118002110910108000010000000005020116112003580000102003920039200392003920039
800242003814900001801232580010108000010801965064000002001902003820038999631001880010208000020800002003820038118002110910108000010000000005020116112003580000102003920039200392003920039
8002420038150000000392580010108000010800005064000002001902003820038999631001880010208000020800002003820038118002110910108000010000000005020116112003580000102003920039200392003920039
8002420038150000090392580010108000010800005064000002001902003820038999631001880010208000020800002003820038118002110910108000010000000205020116112003580000102003920039200392003920193
8002420038150000000392580010108000010800005064000002001902003820038999631001880010208000020800002003820038118002110910108000010000000005020227112003580000102003920039200912010020039
8002420089150000000392580010108000010800005064000002001902003820038999631001880010208000020800002003820038118002110910108000010000000005020216112003580000102003920039200392003920039