Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMGE (vector, 4S)

Test 1: uops

Code:

  fcmge v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371696116872510001000100026535420182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000973116111787100020382038203820382038
100420371606116872510001000100026468020182037203715723189510001000200020372037111001100000973116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100006073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
10042037153906116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  fcmge v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000611968725101001001000010010000500284768012001820037200371842226187451010020010000200200002003720037111020110099100100100001001071011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720084111020110099100100100001000071011611197910100001002003820038200382003820038
102042003714900061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000371011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001001071011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001001071011611197910100001002003820038200382003820038
102042003715000061196874410100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000371011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100011471011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000371011611197910100001002003820038200382003820038
1020420037150000251196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001001717471011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500002000033919687251001212100001210000602847680120018200372003718444318767100122010000202000020037200371110021109101010000100000006422162219785010000102003820038200382003820038
10024200371500000000070719687251001010100001010000502847680120018200372003718444718767101632010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
10024200371500000000013819687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006423162219785410000102003820038200382003820038
1002420037150000000008219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219787010000102003820038200382003820038
10024200371500000000012619687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100010006402162219785010000102003820038200382003820038
1002420037150000000008219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219787010000102003820038200382003820038
1002420037150000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fcmge v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000010319687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
102042003715000000103196872510100100100001001000050028476801200180200372003718422318745101002001000020020000200372003711102011009910010010000100000000710216221979119100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
10204200371500000038219687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000100071021622197910100001002003820038200382003820038
10204200371500000021219687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
1020420037150000008219687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
1020420037150000008219687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
10204200371500000010319687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
10204200371500000010319687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715001781968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715006311968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715001031968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715501511968725100101010000101000050284768012001820037201331844531876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162619785010000102003820038200382003820038
10024200371500821968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162619785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162519785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162319785010000102003820038200382013220038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010106402162219785010000102003820038200382003820038
100242003715002231968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fcmge v0.4s, v8.4s, v9.4s
  fcmge v1.4s, v8.4s, v9.4s
  fcmge v2.4s, v8.4s, v9.4s
  fcmge v3.4s, v8.4s, v9.4s
  fcmge v4.4s, v8.4s, v9.4s
  fcmge v5.4s, v8.4s, v9.4s
  fcmge v6.4s, v8.4s, v9.4s
  fcmge v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200601500040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511021611200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
80204200381500082258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039201452003920039
8020420038150098425801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000005130511011611200350800001002003920039200392003920039
80204200381500061258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000100511011611200350800001002003920039200392003920039
802042003815000515258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011612200350800001002003920039200392003920039
802042003815000390258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004715000003925800101080000108000050640000120019200382003810005310018800102080000201600002003820038118002110910108000010000502011601120035080000102003920039200392003920039
80024200381500000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000502011601120035080000102003920039200392003920039
80024200381500000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000502021601120035080000102003920039200392003920039
80024200381500000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000502011641120035080000102003920039200392003920039
80024200381500000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000502011601120035080000102003920039200392003920039
8002420038150000132392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000502011601120035080000102003920039200392003920039
80024200381500000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010004502011601120035080000102003920039200392003920039
80024200381500000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000502011601120035080000102003920039200392003920039
80024200381500030392580010108000010800005064000012001920087200389996310018800102080000201600002003820038118002110910108000010000502011601120035080000102003920039200392003920039
800242003815000008752580198128000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000502011601120035080000102003920039200392003920039