Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMGT (scalar, D)

Test 1: uops

Code:

  fcmgt d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026596312018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  fcmgt d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500006619687251010010010000100100005002847680200182003720037184220318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000059019687251010010010000100100005002847680200182003720037184220318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680200182003720037184220318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500006119687251010011110000100100005002847680200182003720037184220318745101002001000020020000200372003711102011009910010010000100009071011612198250100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680200182003720037184220318745101002001000020020000200372003711102011009910010010000100003071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680200182003720037184220318745101002001000020020000200372003711102011009910010010000100010071011611197910100001002003820038200382003820038
102042003715000072619687251010010010000100100005002847680200182003720037184220318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680200182003720037184220318745101002001000020020000200372003711102011009910010010000100006071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680200182003720037184220318745101002001000020020000200372003711102011009910010010000100011983071011611197910100001002003820038200382003820038
102042003715000961196872510100100100001021000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000036074111611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)daddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000064031602219785010000102003820038200382003820038
10024200371500456119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010020064021602219785010000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000064021602219785010000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010010064021602219785010000102003820038200382003820038
1002420037150006119687251001011100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010003064021602219785010000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010003064021602219785010000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000064021602219785010000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000064021602219785010000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000064021602219785010000102003820038200382003820038
1002420037150006119687251001012100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010006064021602219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fcmgt d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500061196542510100125100001251000062628476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001001071011611197910100001002003820038200382003820038
10204200371500061196874410100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010009971011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001001071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007571011611197910100001002003820038200382003820038
102042003715090611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010004571011711197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242008415000000010519687251001010100001010000502847680020018200372003718444318767100102010000202000020084200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010152502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000000014519687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000000017019687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000000021219687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100016402162219785010000102003820038200382003820038
100242003715000000088319687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fcmgt d0, d8, d9
  fcmgt d1, d8, d9
  fcmgt d2, d8, d9
  fcmgt d3, d8, d9
  fcmgt d4, d8, d9
  fcmgt d5, d8, d9
  fcmgt d6, d8, d9
  fcmgt d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150000014525801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051103161120035800001002003920039200392003920039
8020420038150000067025801001008000010080000500640000020019200382003899903999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
8020420038149000012425801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000200051101161120035800001002003920039200392003920039
8020420038150000018725801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
8020420038150000010725801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
8020420038150000014525801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000013051101161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
802042003815000008225801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
8020420038150000014925801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101162220035800001002003920039200392003920039
80204200381500000187258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000015051101162220035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020516672003580000102003920039200392003920039
80024200381506392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020416642003580000102003920039200392003920039
80024200381490392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020516662003580000102003920039200392003920039
8002420038150312602580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020416742003580000102003920039200392003920039
80024200381500392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002210910108000010005020616672003580000102003920039200392003920039
80024200381500392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020316432003580000102003920039200392003920039
80024200381490392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020416432003580000102003920039200392003920039
8002420038150315392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020416442003580000102003920039200392003920039
80024200381500394880010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020416432003580000102003920039200392003920039
800242003815018392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020416472003580000102003920039200392003920039