Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMGT (scalar, H)

Test 1: uops

Code:

  fcmgt h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715961168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
10042037153061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100073116121787100020382038203820382038

Test 2: Latency 1->2

Code:

  fcmgt h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500033519687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071021611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500016819687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000056728476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000710116111979114100001002003820038200382003820038
10204200371500012619687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100001071011611197910100001002003820038200382003820038
10204200371500012419687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000120726196872510010101000010100005028476802001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476802001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102011720038201322008620133
10024200831511010156061196872510010101000010100005028476802001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476802001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476802001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476802001802003720037184443187671001020101632020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476802001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476802001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150000000812196872510010101000010100005028476802001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476802001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fcmgt h0, h1, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000056319687251012710010000100100005002847680020018200852003718422818745101002021016520020000200372003711102011009910010010000100000710116111979120100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500003461968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010003071011621198250100001002003820038200382003820038
1020420037150110821968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010003071011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002142000020037200372110201100991001001000010030071011611197910100001002003820038200382003820038
1020420037150000611968725101381001000010010000500284768012001820037200371842631874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000363611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010003071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500039119687251001010100001010000502847680200180200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200180200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200180200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715004116119687251001010100001010000502847680200183200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502848066200180200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200180200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200180200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200180200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200180200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200180200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fcmgt h0, h8, h9
  fcmgt h1, h8, h9
  fcmgt h2, h8, h9
  fcmgt h3, h8, h9
  fcmgt h4, h8, h9
  fcmgt h5, h8, h9
  fcmgt h6, h8, h9
  fcmgt h7, h8, h9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fa9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200601500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051105161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051261161120035800001002003920039200392003920039
802042003815036402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000351101161120035800001002003920039200392003920039
80204200381506402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150447402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381509402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)dfe0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005024351643320035080000102003920039200392003920039
800242003815003392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005024341643320035080000102003920039200392003920039
800242003815000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005024341644320035080000102003920039200392003920039
800242003815000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005024331634320035080000102003920039200392003920039
800242003815000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005024341634320035080000102011120039201002003920039
80024200381500039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001001505024341643320035080000102003920039200392003920039
800242003815006392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005024341634320035080000102003920039200392003920039
800242003815000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005024341624320035080000102003920039200392003920039
800242003815000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005024331643320035080000102003920039200392003920039
800242003815000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005024331643320035280000102003920039200392003920039