Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMGT (scalar, zero, H)

Test 1: uops

Code:

  fcmgt h0, h0, #0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)183f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500611686251000100010002645210201820372037157131895100010001000203720371110011000000073216221786100020382038203820382038
100420371500611686251000100010002645211201820372037157131895100010001000203720371110011000000073216221786100020382038203820382038
1004203715106116862510001000100026452102018203720371571318951000100010002037203711100110000002473216221786100020382038203820382038
100420371501611686251000100010002645211201820372037157131895100010001000203720371110011000001073216221786100020382038203820382038
1004203716001561686251000100010002645211201820372037157131895115210001000203720371110011000000673216221786100020382038203820382038
100420371500611686251000100010002645210201820372037157131895100010001000203720371110011000000073216221786100020382038203820382038
100420371500611686251000100010002645210201820372037157131895100010001000203720371110011000000073216221786100020382038203820382038
1004203716001561686251000100010002645211201820372037157131895100010001000203720371110011000000073216221786100020382038203820382038
100420371600611686251000100010002645210201820372037157131895100010001000203720371110011000000073216221786100020382038203820382038
1004203716001561686251000100010002645211201820372037157131895100010001000203720371110011000000073216221786100020382038203820382038

Test 2: Latency 1->2

Code:

  fcmgt h0, h0, #0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000007102162219791100001002003820038200382003820038
1020420037150000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000243007102162219791100001002003820038200382003820038
1020420037150000441196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000010017102162219791100001002003820038200382003820038
102042003715000061196862510100128100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000003007102162219791100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000090007102162219791100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000007102162219791100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000007102162219791100001002003820038200382003820038
1020420037150000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000190007102162219791100001002003820038200382003820038
102042003715000061196862510100100100001001015250028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000010007102162219791100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000007102162219791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)030e1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000611968625100611010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010300640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010010640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010010640216221978610000102003820038200382003820038
100242003715009611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010013640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
1002420037150003461968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521020018200372003718443251876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  fcmgt h0, h8, #0
  fcmgt h1, h8, #0
  fcmgt h2, h8, #0
  fcmgt h3, h8, #0
  fcmgt h4, h8, #0
  fcmgt h5, h8, #0
  fcmgt h6, h8, #0
  fcmgt h7, h8, #0
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005015111029258010810080008100800205006401320200192003820038997769989801202008003220080032200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039
802042003815011029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039
8020420038150110138258010810080008100800205006401320200192003820038997769989801202008003220080032200382003811802011009910010080000100001611151181161120035800001002003920039200392003920039
802042003815011092258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039
802042003815011052258010810080008100800205006401320200192003820038997769989801202008003220080032200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039
802042003815011052258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039
802042003815011052258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100020011151181161120035800001002003920039200392003920039
802042003815011029258010810080008100800205006401320200192003820038997769989801202008003220080032200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039
802042003815011029258010810080008100800205006401320200192003820038997769989801202008003220080032200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039
8020420038150110292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000033011151181161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005115000001042580010108000010800005064000020019200382003899963100188001020800002080000200382003811800211091010800001000000050201161120035080000102003920039200392003920039
80024200381500000392580010108000010800005064000020019200382003899963100188001020800002080000200382003811800211091010800001000000050201161120035080000102003920039200392003920039
800242003815000003972580010108000010800005064000020019200382003899963100188001020800002080000200382003811800211091010800001000000050201161120035080000102003920039200392003920039
80024200381500000602580010108000010800005064000020019200382003899963100188001020800002080000200382003811800211091010800001000000050201161120035080000102003920039200392003920039
800242003815000001232580010108000010800005064000020019200382003899963100188001020800002080000200382003811800211091010800001000000050201161120035080000102003920039200392003920039
8002420038150000181022580010108000010800005064000020019200382003899963100188001020800002080000200382003811800211091010800001000000050201161120035080000102003920039200392003920039
800242003815000001232580010108000010800005064000020019200382003899963100188001020800002080000200382003811800211091010800001000000050201161120035080000102003920039200392003920039
800242003815000005922580010108000010800005064000020019200382003899963100188001020800002080000200382003811800211091010800001000000050201161120035080000102003920039200392003920039
80024200381500000392580010108000010800005064000020019200382003899963100188001020800002080000200382003811800211091010800001000000050201161120035080000102003920039200392003920039
8002420038150000125502580010108000010800005064000020019200382003899963100188001020800002080000200382003811800211091010800001000000050201161120035080000102003920039200392003920039