Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMGT (vector, 4S)

Test 1: uops

Code:

  fcmgt v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150105168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203716061168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715082168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  fcmgt v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715045061196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100007102161119791100001002003820038200382003820038
1020420037150468061196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715012061196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150120726196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715024061196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371503917661196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371499061196872510100100100001001000050028476801200182003720037184220318745101002001000020020334200372003711102011009910010010000100037101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000540611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000210611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371500300611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001002000640216221978510000102003820038200382003820038
10024200371500000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371500000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371500000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371500000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371500000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000661216221978510000102008420086200862008520038
10024200371501100611968725100101110000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000662224321978510000102008620085200382003820038
10024200371500000611968725100101010000101000060284896312001820037200371844403187671001020100002020000200372003711100211091010100001000020640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fcmgt v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150008219687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000019207101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001004034037101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100001007101161119791100001002003820038200382003820038
10204200371500072619687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037149006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100001037101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000059037101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000037101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001037000640316221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020084200371110021109101010000101000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000101000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715000072619687441001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000102300640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fcmgt v0.4s, v8.4s, v9.4s
  fcmgt v1.4s, v8.4s, v9.4s
  fcmgt v2.4s, v8.4s, v9.4s
  fcmgt v3.4s, v8.4s, v9.4s
  fcmgt v4.4s, v8.4s, v9.4s
  fcmgt v5.4s, v8.4s, v9.4s
  fcmgt v6.4s, v8.4s, v9.4s
  fcmgt v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f5051schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005915104002580100100800001008000050064000012001902003820038997339996801002008000020016000020038200381180201100991001008000010001051104161120035800001002003920039200392003920039
802042003815004002580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815004002580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010001051101161120035800001002003920039200392003920039
8020420038150312602580100100800001008000050064000012001902003820038997339996801002008000020016000020038200381180201100991001008000010001051101161120035800001002003920039200392003920039
802042003815004002580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010002351101161120035800001002003920039200392003920039
802042003815004002580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010002051101161120035800001002003920039200392003920039
802042003815004002580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815004002580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000051101160120035800001002003920039200392003920039
802042003815004002580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815004002580100100800001008000050064000002001902003820038997339996801002008013620016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)193f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420047150000039258001010800001080000506400002001920038200389996310018800102080000201600002003820048118002110910108000010005020316542003580000102003920039201402003920039
8002420038150000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010005020316442003580000102003920039200392003920039
8002420038150000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010005020517552003580000102003920039200392003920039
8002420038150000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010005020316442003580000102003920039200392003920039
8002420038150000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010005020216442003580000102003920039200392003920039
8002420038150000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010005020516342003580000102003920039200392003920039
80024200381500000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100905020216342003580000102003920039200392003920039
8002420038150000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010005020316352003580000102003920039200392003920039
8002420038150000039258001010800001080000506400002001920038200389996310018800102080000201602642003820038118002110910108000010005020516552003580000102003920039200392003920039
8002420038150000039258001010800001080000506400002001920038200389996310046800102080000201600002003820038118002110910108000010005020316342003580000102003920039200392003920039