Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMLA (vector, 2D)

Test 1: uops

Code:

  fcmla v0.2d, v1.2d, v2.2d, #90
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100440373006134072510001000100053190814018403740373258338951000100030004037403711100110000073216123473100040384038403840384038
1004403730126134072510001000100053190814018403740373258338951000100030004037403711100110000073116113473100040384038403840384038
100440373006134072510001000100053190814018403740373258338951000100030004037403711100110000073116113473100040384038403840384038
100440373008434072510001000100053190804018403740373258338951000100030004037403711100110000073116113473100040384038403840384038
100440373006134072510001000100053190814018403740373258338951000100030004037403711100110000073216123473100040384038403840384038
100440373008434072510001000100053190814018403740373258338951000100030004037403711100110000073116113473100040384038403840854038
100440373106133982510001000100053190814018403740373258338951000100030004037403711100110000073116113473100040384038403840384038
100440373006134072510001000100053190814018403740373258338951000100030004037403711100110000073116113473100040384038403840384038
100440373006134072510001000100053190814018403740373258338951000100030004037403711100110000073116113549100040384038403840384038
100440373006134072510001000100053190814018403740373258338951000100030004037403711100110000973116113473100040384038403840384038

Test 2: Latency 1->1

Code:

  fcmla v0.2d, v1.2d, v2.2d, #90
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204400373000000061394072510100100100001001000050057069081400180400374003738108033874510100200100002003000040037400371110201100991001001000010000090671013162239479100001004003840038400384003840038
10204400373000000061394072510100100100001001000050057069080400180400374003738108033874510100200100002003000040037400371110201100991001001000010000070971012162239479100001004003840038400384003840038
10204400373000000061394072510100100100001001000050057069080400180400374003738108033874510100200100002003000040037400371110201100991001001000010000070971012162239479100001004003840038400384003840038
10204400372990000061394072510100100100001001000050057069080400180400374003738108033874510100200100002003000040037400371110201100991001001000010000010971012162239479100001004003840038400384003840038
102044008630000000613940725101001001000010010000500570690804001804003740037381080338745101002001000020030000400374003711102011009910010010000100000801271012162239479100001004003840038400384003840038
102044003730000000613940725101001001000010010000500570690804001804003740037381080338745101002001000020030000400374003711102011009910010010000100000109071012162239479100001004003840038400384003840038
102044003729900000613940725101001001000010010000500570690804001804003740037381080338745101002001000020030000400374003711102011009910010010000100000120971012162239479100001004003840038400384003840038
1020440037300000300763940725101001001000010010000500570690804001804003740037381080338745101002001000020030000400374003711102011009910010010000100000140671012162239479100001004003840038400384003840038
10204400372990000061394072510100100100001001000050057069080400180400374003738108033874510100200100002003000040037400371110201100991001001000010000090371012163239479100001004003840038400384008540038
1020440037300000003723940725101001001000010010000500570690804001804003740037381080338745101002001000020030000400374003711102011009910010010000100000100971212162239479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002440037300006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100002006402162239473010000104008540086400384003840038
1002440037300006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
1002440037300006139407251001010100001010000505706908040018400374003738130338767100102010000203000040037400371110021109101010000100000006403162239473010000104003840038400384003840038
100244003730000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000312606402162239473010000104003840038400384003840038
1002440037300006139407251001010100001010000505706908040018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
10024400373000061394072510010101000010100005057069080400184003740037381303387671001020100002030000400374003711100211091010100001000127006402162239473010000104003840038400384003840038
1002440037300006139407251001010100001010000505706908140018400374003738130338767100102210000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
1002440037300006139407251001010100001010000505706908140054400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
100244003730000115639407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
10024400373000061394072510010101000610100005057069081400184003740037381303387671001020100002030000400374003711100211091010100001000017906403162239474010000104003840038400384003840038

Test 3: Latency 1->2

Code:

  fcmla v0.2d, v0.2d, v1.2d, #90
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020440037299061394072510100100100001001000050057069081400180400374003738108033874510100200100002003000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069080400180400374003738108033874510100200100002003000040229400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037300076394072510100100100001001000050057069080400180400374003738108033874510100200100002003000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069080400180400374003738108033874510100200100002003000040037400371110201100991001001000010000071011611395260100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069080400180400374003738108033874510100200100002003000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037299061394072510100100100001001000050057069080400180400374003738108033874510100200100002003000040037400371110201100991001001000010000071011611394792100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069080400180400374003738108033874510100200100002003000040229400811110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069080400180400374003738108033874510100200100002003000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037299061394072510100100100001001000050057069080400180400374003738108033874510100200100002003000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037299061394072510100100100001001000050057069080400180400374003738108033874510100200100002003000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100244003730000000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000006402162239473010000104003840038400384003840038
100244003730000000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000006402162239473010000104003840038400384003840038
100244003730000000613940725100101010000101015350570690814001840037400373813033876710010201000020300004003740037111002110910101000010000006402162439512010000104003840038400384003840038
100244003730000000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000006402162239473010000104003840038400384003840038
100244003730000000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000006402162239473010000104003840038400384003840038
1002440037299000007263940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000006402162239473010000104003840038400384003840038
1002440037300000003593940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000006402162239473010000104003840038400384003840038
100244003730000000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037511002110910101000010000006402162239473010000104003840038400384003840038
100244003729900000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000006402162239473010000104003840038400384003840038
100244003730000000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000006402162239473010000104003840038400384003840038

Test 4: Latency 1->3

Code:

  fcmla v0.2d, v1.2d, v0.2d, #90
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020440037300311104613940725101001001000010010000500570690814001840037400373810803387451010020010000200300004003740037111020110099100100100001001071031622394790100001004003840038400384003840038
10204400373000012613940725101001001000010010000500570690814001840037400373810803387451010020010000200300004003740037111020110099100100100001000071021622394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690814001840037400373810803387451010020010000200300004003740037111020110099100100100001000071021622394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690814001840037400373810803387451010020010000200300004003740037111020110099100100100001000371021622394790100001004003840038400384003840038
1020440037299000613940725101001001000010010000500570690814001840037400373810803387451010020010000200300004003740037111020110099100100100001000071021622394790100001004003840038400384003840038
102044003729900552613940725101001001000010010000500570690814001840037400373810803387451010020010000200300004003740037111020110099100100100001000071021622394790100001004003840038400384003840038
1020440037299000613940725101001001000010010000500570690814001840037400373810803387451010020010000200300004003740037111020110099100100100001000071021622394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690814001840037400373810803387451010020010000200300004003740037111020110099100100100001000071021622395380100001004003840038400384003840038
102044008430000654613940725101001001000010010000500570690814001840037400373810803387451010020010000200300004003740037111020110099100100100001000071021622394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690814001840037400373810803387451010020010000200300004003740037111020110099100100100001000071021622394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03091e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024400373000006139407251001010100001010000505706908140018400374003738130338767101592010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
10024400372990006139407251001010100001010000505706908040018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
10024400373000006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
10025400373000006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
10024400373000006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
10024400373000006139407251001010100001010000505706908040018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
100244003730000072639407251001010100001010000505706908040018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
10024400373000006139407251001010100001010000505706908040018400374003738130338767100102010000203000040037400371110021109101010000100030006402162239473010000104003840038400384003840038
10024400373000006139407251001010100001010000505706908040018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239549010000104003840038400384003840038
10024400372990006639407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fcmla v0.2d, v8.2d, v9.2d, #90
  movi v1.16b, 0
  fcmla v1.2d, v8.2d, v9.2d, #90
  movi v2.16b, 0
  fcmla v2.2d, v8.2d, v9.2d, #90
  movi v3.16b, 0
  fcmla v3.2d, v8.2d, v9.2d, #90
  movi v4.16b, 0
  fcmla v4.2d, v8.2d, v9.2d, #90
  movi v5.16b, 0
  fcmla v5.2d, v8.2d, v9.2d, #90
  movi v6.16b, 0
  fcmla v6.2d, v8.2d, v9.2d, #90
  movi v7.16b, 0
  fcmla v7.2d, v8.2d, v9.2d, #90
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204200891500024029258011610080016100800285006401960200462006520065612801282008002820024008420065200651116020110099100100160000100001111011911611200621600001002006620066200662006620066
160204200651500015029258011610080016100800285006401961200462006520065612801282008002820024008420065200651116020110099100100160000100001111011911611200621600001002006620066200662006620066
16020420065150100029258011610080016100800285006401961200462006520065612801282008002820024008420065200651116020110099100100160000100001111011911611200621600001002006620066200662006620066
16020420065150003029258011610080016100800285006401961200462006520065612801282008002820024008420065200651116020110099100100160000100001111011911611200621600001002006620066200662006620066
16020420065151000040258010010080000100800005006400001200462006520065323801002008000020024000020065200651116020110099100100160000100000001011221622200621600001002006620066200662006620066
16020420065150000040258010010080000100800005006400001200462006520065323801002008000020024000020065200651116020110099100100160000100000001011221622200621600001002006620066200662006620066
16020420065150000040258010010080000100800005006400001200462006520065323801002008000020224000020065200651116020110099100100160000100000001011221622200621600001002006620066200662006620066
16020420065150000040258010010080000100800005006400001200462006520065323801002008000020024000020065200651116020110099100100160000100000001011221622200621600001002006620066200662006620066
16020420065150000040258010010080000100800005006400001200462006520065323801002008000020024000020065200651116020110099100100160000100000001011221622200621600001002006620066200662006620066
16020420065150000040258010010080000100800005006400001200462006520065323801002008000020024000020065200651116020110099100100160000100000001011221622200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)181e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch mispred nonspec (cb)cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242011315002011000462780012128000012800006264000011520044200632006331128001220800002024000020063200631116002110910101600001070100451662133363222828200602412160000102006420064200642006420064
1600242006315012002001762980012128000012800006264000001102004420063200633238001220800002024000020063200631116002110910101600001000100451672118363222723200602412160000102006420064200642006420064
1600242006315013002001582980012128000012800006264000001102004420063200633238001220800002024000020063200631116002110910101600001000100571672130363221931200602412160000102006420064200642006420064
16002420063150120020007292980012128000012800006264000001102011020063200633238001220800002024000020063200631116002110910101600001000100671662128363222930200602412160000102006420064200642006420064
1600242006315013002001642980012128000012800006264000001102004420063200633238001220800002024000020063200631116002110910101600001000100501672122363223018200602412160000102006420064200642006420064
1600242006315013003000702980012128000012800006264000001102004420063200633238001220800002024000020063200631116002110910101600001000100571672129363223030200602412160000102006420064200642006420064
1600242006315012003001642980012128000012800006264000001102004420063200633238001220800002024000020063200631116002110910101600001000100561662127363422828200602412160000102006420064200642006420064
1600242006315012002001762980012128000012800006264000001102004420063200633238001220800002024000020063200631116002110910101600001000100551672127363221629200602412160000102006420064200642006420064
160024200631501300302117412980012128000012800006264000001102004420063200633238001220800002024000020063200631116002110910101600001000100431662123363223018200602412160000102006420064200642006420064
16002420063150120021180762980012128000012800006264000001102004420063200633238001220800002024000020063200631116002110910101600001000100511662118363222723200602412160000102006420064200642006420064

Test 6: throughput

Count: 16

Code:

  fcmla v0.2d, v16.2d, v17.2d, #90
  fcmla v1.2d, v16.2d, v17.2d, #90
  fcmla v2.2d, v16.2d, v17.2d, #90
  fcmla v3.2d, v16.2d, v17.2d, #90
  fcmla v4.2d, v16.2d, v17.2d, #90
  fcmla v5.2d, v16.2d, v17.2d, #90
  fcmla v6.2d, v16.2d, v17.2d, #90
  fcmla v7.2d, v16.2d, v17.2d, #90
  fcmla v8.2d, v16.2d, v17.2d, #90
  fcmla v9.2d, v16.2d, v17.2d, #90
  fcmla v10.2d, v16.2d, v17.2d, #90
  fcmla v11.2d, v16.2d, v17.2d, #90
  fcmla v12.2d, v16.2d, v17.2d, #90
  fcmla v13.2d, v16.2d, v17.2d, #90
  fcmla v14.2d, v16.2d, v17.2d, #90
  fcmla v15.2d, v16.2d, v17.2d, #90
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03191e373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400593120043610251601001001600001001600005001707603400214004040040199730319998160100200160000200480000400404004011160201100991001001600001000000010110916994003701600001004004140044400414004140041
16020441190317000424485251601001001600001001600005001280000400214004040040199730319998160100200160000200480000411904004311160201100991001001600001000001010110816884120201600001004004140041400414120640041
16020441190309004372602516010010016000010016000050012800004118640040400401997337319998160100200160000200480000400404004011160201100991001001600001000000010110916994003701600001004004140041400414119140041
160204400403080004202516010010016000010016000050012800004117141190412051997303199981601002001600002004800004004041190111602011009910010016000010000000101101116944003701600001004004140041400414119141191
16020440040309000420251601001001601421001600005001280000423084004040040199730319998160100200160000200480000400404004011160201100991001001600001000000010110816884003701600001004120640041400414004140041
16020440040309000420251601001001600001001600005002646333400224004041190199730319998160100200160000200480000400404004011160201100991001001600001000000010110916894118701600001004004140041400414232841206
16020440040308000610251601001001600001001600005005717939400214119041205211110319998160100200160000200480000400404004011160201100991001001600001000000010110916994003701600001004119141206400414004140041
16020442281300000420251601001001600001001600005001280000411714004040040211090319998160100200160000200480000411904120511160201100991001001600001000000010110916994004001600001004119141206400414004141191
16020440040299000420251601431001600001001600005001280000400214120540040199730319998160100200160000200480000412044004011160201100991001001600001000000010110816994120201600001004004140041422954120540042
160204400403080005170251601001001600001001600005001280000411864004040040199730321163160100200160000200480000400404004011160201100991001001600001000000010110916994003701600001004004140041400414004140044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2576

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e373a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002440050300100015303516001110160000101600005057106540110400214231840040199960321206160010201600002048000042318400401116002110910101600001030001002316412316322291640039317160000104004140041423194004140041
16002441229316010530738970251600701016005310160000501280000111041207412264122621141253212061600102016000020480000412264122611160021109101016000010960010025166229163121728400371611160000104004140041423194004142295
160024423182991101059457625160045101601021016000050572804711104121041226400402114103200201600102016000020480000400404043131160021109101016000010400010024166225163222125423151611160000104122741227412274122740041
160024422813001100053025160070101600531016000050128000001104002141226412262114103211991600102016000020480000412194122611160021109101016000010890010023166120163222617400393111160000104004140041400414004140041
160024400403171101053025160010101600001016000050128000001104002140040423182224403222981600102016000020480000400404122611160021109101016000010990010025167226161221526412233114160000104004142319400414231940041
160024400403170000065457625160010101600001016000050128000011104120741219400402113603211831600102016000020480000400404004011160021109101016000010430010023167127161221626423153111160000104004141227412274122740041
16002440040300101201850251600281016000010160000505868333011040021400404004019996032002016001020160000204800004004040040111600211091010160000102012001002513722516322262642315318160000104231940041423194004140041
16002440040308110531674576251600701016000110160000501280000011040021412264004021141253200201600102016000020480000412264122611160021109101016000010800010024167121163122617400371612160000104231940041400414004140041
16002440040317110016589702516005310160000101600005058683331110422994231840040199960322298160010201600002048000042318400401116002110910101600001080101002216712616121202540037318160000104122741227412274122740041
160024400403090100165458925160011101600001016000050128000001104002140040400402224403222981600102016000020480000423184004011160021109101016000010600010025167226163221525400373111160000104004142319400414231940041