Firestorm: FCMLA (vector, by element, 4H) measurements

Code:

  fcmla v0.4h, v1.4h, v2.h[1], #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	3	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	9	103	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fcmla v0.4h, v1.4h, v2.h[1], #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	1	1	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38115	0	6	38741	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	720	0	1	16	1	1	39493	10000	100	40038	40038	40038	40038	40038
10204	40037	300	1	1	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38115	0	6	38741	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	1	16	1	1	39493	10000	100	40038	40038	40038	40038	40038
10204	40037	300	1	1	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	3	16	4	3	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	3	16	3	3	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	9	0	0	61	39407	104	10136	102	10000	100	10000	500	5706908	1	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	3	16	3	3	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40084	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	3	16	3	3	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	6	0	0	0	0	710	1	3	16	3	3	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	6	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	3	16	3	3	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	3	16	3	3	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10148	500	5706908	1	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	3	16	3	3	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	12	0	66	39407	25	10010	10	10000	10	10148	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	3	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	2582	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	3	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	21	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	3	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	3	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fcmla v0.4h, v0.4h, v1.h[1], #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	299	0	0	0	103	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10174	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	3	573	264	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	726	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	1	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	6	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	0	0	0	161	39407	25	10016	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	4	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	4	4	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30486	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	4	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	3	4	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	4	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	4	4	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	726	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	4	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	3	4	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	4	4	39473	0	10000	10	40038	40038	40085	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	1	0	0	640	4	16	4	4	39473	0	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fcmla v0.4h, v1.4h, v0.h[1], #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	299	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	310	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10006	100	10000	500	5706908	0	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	1	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10116	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	25	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	371	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	371	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	2	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	347	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	1	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	347	0	0	0	0	0	0	0	726	39407	25	10010	10	10000	14	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10159	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	1	0	0	0	640	2	16	2	2	39547	0	10000	10	40038	40038	40038	40038	40038
10024	40037	322	0	0	0	0	0	0	0	726	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	4	0	3	0	663	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	321	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	59	0	0	0	640	2	16	2	2	39473	0	10000	10	40085	40038	40038	40038	40038
10024	40037	322	0	0	0	0	0	0	0	103	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	22	0	3	0	640	7	73	4	2	39473	2	10000	10	40882	40895	40978	40989	40937
10024	40037	321	1	0	0	0	0	0	0	2526	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	7	0	6	0	640	3	80	2	2	39509	0	10000	10	40086	40180	40181	40181	40178
10024	40133	311	0	0	0	0	0	0	0	896	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40131	40452	38192	70	39048	12534	28	12593	24	37782	40782	40833	17	1	10021	10	9	10	10	10000	10	2	2	3	0	30	0	46760	0	788	2	32	3	2	39581	6	10000	10	40889	40885	40878	40835	40889
10024	40840	312	1	0	17	16	2127	1584	0	13750	39236	375	10125	11	10108	20	12664	92	5730640	0	40648	40887	40932	38215	71	39160	12831	28	13073	28	38940	40928	40885	19	1	10021	10	9	10	10	10000	10	0	0	0	0	6	2	65027	12	1003	3	145	2	2	39744	2	10000	10	40417	40563	40462	40509	40794

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fcmla v0.4h, v8.4h, v9.h[1], #90
  movi v1.16b, 0
  fcmla v1.4h, v8.4h, v9.h[1], #90
  movi v2.16b, 0
  fcmla v2.4h, v8.4h, v9.h[1], #90
  movi v3.16b, 0
  fcmla v3.4h, v8.4h, v9.h[1], #90
  movi v4.16b, 0
  fcmla v4.4h, v8.4h, v9.h[1], #90
  movi v5.16b, 0
  fcmla v5.4h, v8.4h, v9.h[1], #90
  movi v6.16b, 0
  fcmla v6.4h, v8.4h, v9.h[1], #90
  movi v7.16b, 0
  fcmla v7.4h, v8.4h, v9.h[1], #90

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20091	150	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	0	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	1	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	5	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80104	100	80000	500	640000	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	0	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	4	15	10111	0	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	5	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	0	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	5	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	1	0	10111	0	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	186	40	25	80100	100	80000	100	80000	500	640000	0	5	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	0	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	705	25	80100	100	80000	100	80000	500	640000	1	0	20046	20065	20065	3	23	80100	200	80000	200	240327	20065	20091	2	1	160201	100	99	100	100	160000	100	1	0	10111	0	0	1	16	1	1	20062	0	160000	100	20150	20148	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	1	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	0	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	0	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20071	150	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	0	1	10	20042	20061	20061	3	23	80012	20	80000	20	240000	20061	20061	1	1	160021	10	9	10	10	160000	10	0	0	3	0	0	0	10027	16	5	2	6	27	2	1	1	4	2	20049	2	20	1	160000	10	20062	20062	20062	20062	20062
160024	20061	150	0	0	0	0	52	29	80012	12	80000	12	80000	62	640000	0	1	0	20033	20061	20061	3	23	80012	20	80000	20	240000	20061	20061	1	1	160021	10	9	10	10	160000	10	0	0	0	4	3	0	10030	16	7	1	4	34	4	2	1	2	4	20049	2	20	1	160000	10	20175	20071	20062	20154	20062
160024	20061	150	0	0	0	0	52	29	80012	12	80000	12	80000	62	640000	0	1	10	20042	20061	20061	3	23	80012	20	80000	20	240000	20061	20061	1	1	160021	10	9	10	10	160000	10	0	0	2	0	506	0	10028	16	7	2	4	34	2	2	2	2	4	20058	2	40	2	160000	10	20062	20062	20062	20062	20062
160024	20061	151	0	0	0	0	52	29	80012	12	80000	12	80000	62	640000	0	0	10	20042	20061	20061	3	23	80012	20	80000	20	240000	20061	20061	1	1	160021	10	9	10	10	160000	10	0	0	1	0	0	0	10031	16	7	2	4	34	2	2	2	4	2	20058	2	40	2	160000	10	20062	20062	20062	20053	20062
160024	20061	153	0	0	0	0	52	27	80012	12	80000	12	80000	62	640000	0	1	10	20033	20061	20061	38	23	80012	20	80000	20	240000	20061	20061	1	1	160021	10	9	10	10	160000	10	0	0	1	0	0	0	10030	16	7	2	5	34	4	2	2	7	7	20058	2	40	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	10	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10027	13	6	1	4	25	2	1	1	2	4	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	10	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	3	0	0	0	10027	13	6	1	2	25	2	1	1	4	2	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	10	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10027	13	6	1	4	25	2	1	1	2	4	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	711	27	80012	12	80000	12	80000	62	640000	1	1	10	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10027	13	6	1	4	25	2	1	1	4	2	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	10	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10027	13	6	1	2	25	2	2	2	5	7	20049	2	20	1	160000	10	20053	20053	20053	20053	20053

Test 6: throughput

Count: 16

Code:

  fcmla v0.4h, v16.4h, v17.h[1], #90
  fcmla v1.4h, v16.4h, v17.h[1], #90
  fcmla v2.4h, v16.4h, v17.h[1], #90
  fcmla v3.4h, v16.4h, v17.h[1], #90
  fcmla v4.4h, v16.4h, v17.h[1], #90
  fcmla v5.4h, v16.4h, v17.h[1], #90
  fcmla v6.4h, v16.4h, v17.h[1], #90
  fcmla v7.4h, v16.4h, v17.h[1], #90
  fcmla v8.4h, v16.4h, v17.h[1], #90
  fcmla v9.4h, v16.4h, v17.h[1], #90
  fcmla v10.4h, v16.4h, v17.h[1], #90
  fcmla v11.4h, v16.4h, v17.h[1], #90
  fcmla v12.4h, v16.4h, v17.h[1], #90
  fcmla v13.4h, v16.4h, v17.h[1], #90
  fcmla v14.4h, v16.4h, v17.h[1], #90
  fcmla v15.4h, v16.4h, v17.h[1], #90

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40063	300	0	0	0	0	0	80	62	0	25	160100	100	160080	100	160000	626	1280000	1	40021	40040	40040	19973	0	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	2	0	0	0	10110	1	16	1	1	42311	25	160000	100	40041	40041	40041	40041	42328
160204	40040	300	0	0	0	0	0	0	42	0	25	160100	125	160000	100	160000	500	1280000	0	40021	40040	40040	22214	0	3	22285	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40037	0	160000	100	42328	40041	40041	40041	40041
160204	40040	299	0	0	0	0	0	0	42	0	25	160100	100	160000	100	160000	500	1280000	1	42308	40040	40040	19973	0	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	16	0	12	0	10112	1	16	1	1	40037	0	160000	100	40192	41118	40041	42328	42297
160204	40040	299	0	0	0	0	0	0	42	0	25	160100	100	160000	100	160000	500	1280000	1	40021	40040	40040	19973	0	3	19998	160100	200	160000	200	480000	40040	42327	1	1	160201	100	99	100	100	160000	100	0	0	2	0	0	0	10110	1	16	1	1	40037	0	160000	100	42315	40041	40041	40041	40041
160204	40040	317	0	0	0	0	0	0	42	0	25	160100	100	160000	100	160000	500	1280000	1	40021	42327	42327	19973	0	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40037	0	160000	100	40041	40041	42328	40041	40041
160204	40040	300	0	0	0	0	0	0	42	0	25	160100	100	160000	100	160000	500	5868895	1	42308	40040	40040	19973	0	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	17	2	3	40037	25	160000	100	42328	40041	40041	40041	40041
160204	40040	300	0	0	0	0	0	0	42	0	25	160100	100	160000	100	160000	500	5868895	0	40021	40040	42327	19973	0	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	42324	0	160000	100	40041	40041	40041	42328	40041
160204	40040	300	0	0	0	0	0	80	61	0	25	160180	100	160080	100	160000	500	5868895	0	42308	40040	40040	19973	0	3	22285	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	43	0	0	0	10110	1	16	1	1	42324	0	160000	100	40041	40041	40041	40041	42328
160204	40040	299	0	0	0	0	0	0	728	8955	25	160180	100	160080	100	160000	500	1280000	1	40021	42327	40040	19973	0	3	22285	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	3	0	0	0	10110	1	16	1	1	40037	25	160000	100	40041	40041	40041	40041	40041
160204	40040	300	0	0	0	0	0	0	41	0	25	160168	125	160000	125	160000	626	1280000	0	40021	40040	40040	22214	0	3	22285	160100	200	160000	200	480000	40040	42327	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	42324	0	160000	100	40041	42295	40041	40041	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	1e	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40226	300	0	0	0	0	53	0	67	4576	25	160063	10	160000	10	160000	50	5868333	1	1	0	42299	40040	42318	22244	0	3	20020	160010	20	160000	20	480000	40040	41219	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	8	3	1	1	28	16	1	1	1	37	38	42315	21	8	160000	10	40041	42319	40041	40041	40043
160024	40040	300	1	0	0	0	0	1	53	4576	25	160010	10	160000	10	160000	50	1280000	1	1	5	41207	40040	40040	19996	25	3	20020	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	8	6	1	1	36	16	1	1	1	35	35	40037	21	8	160000	10	41227	40041	40041	41227	40041
160024	40040	300	1	0	0	0	1	1	73	4589	25	160010	10	160053	10	160000	50	5868333	1	1	5	42299	42318	40040	19996	0	3	20020	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	6	1	0	36	16	1	1	1	24	35	42324	21	8	160000	10	40041	42319	40041	42319	40041
160024	40076	300	1	0	0	0	0	1	53	0	25	160010	10	160000	10	160000	50	5868333	1	1	5	40021	40040	40040	19996	0	3	20020	160010	20	160000	20	480000	40040	42318	1	1	160021	10	9	10	10	160000	10	0	6	0	0	0	10023	8	6	1	1	35	16	1	1	1	25	35	40037	21	8	160000	10	40041	41227	41220	42319	40041
160024	40040	317	1	0	0	0	53	1	47	0	25	160010	10	160000	10	160000	50	1280000	1	1	5	40021	40040	42318	22244	0	3	22298	160010	20	160000	20	480000	42318	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	8	6	1	1	36	16	1	1	1	36	36	40037	21	8	160000	10	41227	41227	41227	41227	40041
160024	40040	300	1	0	0	0	0	1	47	8970	25	160010	10	160000	10	160000	50	1280000	1	1	5	42299	40040	42318	19996	0	3	22298	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	8	6	1	0	25	16	1	1	1	35	25	40037	21	8	160000	10	40041	40041	40041	42319	42319
160024	42318	300	1	0	0	0	53	1	59	0	25	160063	10	160053	10	160000	50	1280000	1	1	5	40021	42318	40040	22208	25	3	20020	160010	20	160000	20	480000	42318	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	8	6	1	1	36	16	1	1	1	37	37	42315	21	8	160000	10	40041	40041	42319	40041	40041
160024	41229	309	1	0	0	0	35	1	73	8970	25	160063	10	160053	10	160000	50	5868333	0	1	5	40021	40040	42318	19996	25	3	22298	160010	20	160000	20	480000	42318	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	11	6	1	1	37	16	1	1	1	38	37	40037	21	8	160000	10	40043	40041	40041	42319	42319
160024	40042	299	1	0	0	0	0	1	53	8970	25	160010	10	160000	10	160000	50	5868333	0	1	5	40021	40040	40040	22244	0	3	20020	160010	20	160000	20	480000	40040	42318	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	8	6	1	1	37	16	1	1	1	28	37	42315	41	8	160000	10	41220	40041	40043	40041	40041
160024	40042	300	1	0	0	0	1	1	79	0	25	160010	10	160000	10	160000	50	1280000	1	1	5	40021	41226	41226	21141	25	3	21206	160010	20	160000	20	480000	40040	42318	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	8	6	1	1	37	16	1	1	1	37	35	40037	21	8	160000	10	41227	41227	41220	42319	40041

FCMLA (vector, by element, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations