Firestorm: FCMLA (vector, by element, 4S) measurements

Code:

  fcmla v0.4s, v1.4s, v2.s[1], #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3a	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	0	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	1	0	0	61	3407	25	1000	1000	1148	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	0	0	149	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	18	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	2	6	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	2	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fcmla v0.4s, v1.4s, v2.s[1], #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	103	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	321	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	4	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	18	0	726	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	84	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10006	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	22	10326	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	9	0	61	39407	25	10010	10	10000	10	10000	50	5708305	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	4	3	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fcmla v0.4s, v0.4s, v1.s[1], #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	299	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	3	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	104	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	742	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	45	1027	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30516	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	23	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	251	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10605	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40085	40084	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	12	0	103	39407	25	10010	10	10000	10	10000	50	5706908	0	40053	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	2	0	0	0	660	2	24	3	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	12	0	61	39407	25	10010	10	10000	10	10148	50	5708304	0	40018	0	40037	40037	38138	3	38787	10160	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	12	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	3	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fcmla v0.4s, v1.4s, v0.s[1], #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	204	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	1	0	6	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	44	0	0	0	739	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	8	0	6	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	14	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	61	39407	107	10119	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	11	0	3	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	15	0	18	0	710	1	16	1	1	39479	0	10000	100	40038	40088	40038	40038	40038
10204	40037	299	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	13	0	9	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	10	0	6	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	8	0	9	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	4	0	3	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	32	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	58	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	6	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	6	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	189	39407	25	10010	10	10000	10	10000	55	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	3	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	1	0	0	12	61	39407	25	10010	10	10024	10	10148	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	15	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	3	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40076
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	6	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	726	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38135	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	4	3	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	15	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fcmla v0.4s, v8.4s, v9.s[1], #90
  movi v1.16b, 0
  fcmla v1.4s, v8.4s, v9.s[1], #90
  movi v2.16b, 0
  fcmla v2.4s, v8.4s, v9.s[1], #90
  movi v3.16b, 0
  fcmla v3.4s, v8.4s, v9.s[1], #90
  movi v4.16b, 0
  fcmla v4.4s, v8.4s, v9.s[1], #90
  movi v5.16b, 0
  fcmla v5.4s, v8.4s, v9.s[1], #90
  movi v6.16b, 0
  fcmla v6.4s, v8.4s, v9.s[1], #90
  movi v7.16b, 0
  fcmla v7.4s, v8.4s, v9.s[1], #90

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20088	151	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	3	23	80100	202	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10111	0	0	2	16	1	1	20062	0	160000	100	20066	20066	20071	20066	20066
160204	20065	152	0	0	0	515	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	6	0	0	10111	5	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10111	0	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	1	0	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	3	23	80210	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	3	0	0	10111	0	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	15	0	0	10111	0	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	3	0	0	10111	5	1	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	5	20114	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	3	0	0	10111	5	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10135	0	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	5	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	0	12	0	0	10111	0	1	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	5	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10111	0	1	1	16	1	1	20062	0	160000	100	20066	20148	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20087	150	1	1	1	3	109	27	80012	12	80000	12	80000	62	640000	1	1	5	20099	20052	20052	12	23	80012	20	80109	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	20	60	0	10042	13	2	1	43	34	2	1	1	19	19	20049	2	40	1	160000	10	20053	20053	20247	20066	20053
160024	20061	150	0	0	0	0	88	27	80012	12	80000	12	80000	62	640000	1	1	10	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	3	0	10042	13	7	1	25	25	4	1	1	20	20	20049	2	20	1	160000	10	20053	20053	20248	20075	20053
160024	20052	150	0	0	0	12	88	27	80012	12	80000	12	80000	62	640000	1	1	10	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	1	9	0	10044	13	7	1	24	25	2	1	1	17	25	20049	2	20	1	160000	10	20053	20053	20230	20066	20053
160024	20052	150	0	0	0	0	88	27	80012	12	80000	12	80000	62	640000	0	1	10	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	3	0	10041	13	7	1	15	25	2	1	2	19	19	20049	2	20	1	160000	10	20053	20053	20258	20066	20053
160024	20061	150	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	10	20042	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	1	111	0	10042	13	8	2	19	25	4	1	1	17	25	20049	2	20	1	160000	10	20053	20053	20228	20075	20053
160024	20052	150	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	10	20033	20052	20052	3	23	80012	20	80000	20	240000	20061	20052	1	1	160021	10	9	10	10	160000	10	1	0	0	10046	13	8	1	20	25	2	1	1	15	20	20049	2	20	1	160000	10	20053	20053	20243	20066	20053
160024	20052	150	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	10	20042	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10042	13	8	1	19	25	2	1	1	21	15	20049	2	20	1	160000	10	20053	20053	20220	20066	20384
160024	20052	150	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	10	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	44	3	0	10038	13	8	1	15	25	2	1	1	19	15	20049	2	20	1	160000	10	20053	20053	20229	20066	20053
160024	20052	150	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	10	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	1	6	0	10047	13	8	1	19	25	2	1	1	26	25	20049	2	20	1	160000	10	20053	20053	20232	20066	20053
160024	20052	150	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	10	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	37	3	0	10038	13	8	1	15	25	2	1	1	19	15	20049	2	20	1	160000	10	20053	20053	20228	20066	20053

Test 6: throughput

Count: 16

Code:

  fcmla v0.4s, v16.4s, v17.s[1], #90
  fcmla v1.4s, v16.4s, v17.s[1], #90
  fcmla v2.4s, v16.4s, v17.s[1], #90
  fcmla v3.4s, v16.4s, v17.s[1], #90
  fcmla v4.4s, v16.4s, v17.s[1], #90
  fcmla v5.4s, v16.4s, v17.s[1], #90
  fcmla v6.4s, v16.4s, v17.s[1], #90
  fcmla v7.4s, v16.4s, v17.s[1], #90
  fcmla v8.4s, v16.4s, v17.s[1], #90
  fcmla v9.4s, v16.4s, v17.s[1], #90
  fcmla v10.4s, v16.4s, v17.s[1], #90
  fcmla v11.4s, v16.4s, v17.s[1], #90
  fcmla v12.4s, v16.4s, v17.s[1], #90
  fcmla v13.4s, v16.4s, v17.s[1], #90
  fcmla v14.4s, v16.4s, v17.s[1], #90
  fcmla v15.4s, v16.4s, v17.s[1], #90

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40060	317	0	0	0	0	17	42	0	25	160100	100	160035	100	160000	500	1280000	0	40021	40040	40040	19973	0	3	22239	160100	200	160000	200	480000	41245	40040	1	1	160201	100	99	100	100	160000	100	0	0	4	0	0	10110	1	16	1	1	41242	160000	100	40041	40041	40041	40041	40041
160204	41245	309	0	0	0	0	0	42	0	25	160100	100	160035	100	160000	500	5721073	0	40021	41245	40040	19973	0	3	19998	160100	200	160000	200	480000	42294	41245	1	1	160201	100	99	100	100	160000	100	0	0	1	0	0	10110	1	16	1	1	40037	160000	100	40041	42295	40041	40041	41246
160204	41245	317	0	0	0	0	54	89	0	25	160135	100	160000	100	160000	500	1280000	1	40021	41245	41245	19973	0	3	22252	160100	200	160000	200	480000	42294	41245	1	1	160201	100	99	100	100	160000	100	0	0	0	3	0	10110	1	16	1	1	40037	160000	100	42328	42282	40043	40041	40041
160204	41245	300	0	0	0	0	0	232	0	58	160100	100	160000	100	160000	500	1280000	1	40021	40040	40040	19973	0	3	22252	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	1	0	0	10110	1	16	1	1	40037	160000	100	40041	42295	40041	40041	40041
160204	40040	299	0	0	0	0	0	1103	8937	25	160100	100	160035	100	160000	500	1280000	1	40021	41245	41245	22198	32	3	21203	160100	200	160000	200	480000	40040	42294	1	1	160201	100	99	100	100	160000	100	0	0	1	0	0	10110	1	16	1	1	40037	160000	100	40041	40041	42310	40041	40041
160204	40040	300	0	0	0	0	0	42	0	25	160100	100	160000	100	160000	500	1280000	0	40021	40040	40040	19973	0	3	21203	160100	200	160000	200	480000	41245	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40037	160000	100	40041	40041	40041	41215	42286
160204	40040	300	0	0	0	0	0	707	0	25	160153	100	160036	100	160000	500	1280000	1	40021	40040	40040	19973	0	3	19998	160100	200	160000	200	480000	41190	41219	1	1	160201	100	99	100	100	160000	100	0	0	4	0	0	10110	1	16	1	1	42291	160000	100	40041	40041	40041	40041	40041
160204	40040	309	0	0	0	0	35	42	4575	25	160100	100	160035	100	160000	500	5721073	1	41226	41245	40040	21151	0	3	21203	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	4	0	0	10110	1	16	1	1	40037	160000	100	40041	40041	40041	40041	40041
160204	42294	300	0	0	0	0	0	42	0	25	160100	100	160000	100	160000	500	1280000	1	42262	42281	40040	19973	0	3	22252	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	2	0	0	10110	1	16	1	1	40037	160000	100	41246	41246	40044	42328	40041
160204	40040	317	0	0	0	0	1	707	0	25	160100	100	160035	100	160000	500	1280000	1	41226	40040	40040	21151	0	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	4	0	0	10110	1	16	1	1	42282	160000	100	42286	42286	40043	40041	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	42281	299	0	0	53	47	4576	25	160045	10	160000	10	160000	50	5868333	1	1	10	40021	40040	40040	19996	0	3	20020	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	3	1	4	16	2	1	1	7	6	40037	20	11	160000	10	40041	40043	40041	42282	40041
160024	40040	300	0	0	0	732	4576	25	160070	10	160000	10	160000	50	5868333	1	1	10	40022	40040	40040	21386	0	3	20021	160010	20	160000	20	480000	40040	40042	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	4	1	7	16	2	1	1	4	3	42292	20	8	160000	10	42319	40041	40043	40041	42319
160024	40040	299	0	0	0	49	8863	25	160011	10	160000	10	160000	50	1280000	1	1	10	40021	42318	40040	19996	0	3	21206	160010	20	160000	20	480000	42302	41226	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	5	1	3	16	2	1	1	4	7	40038	20	8	160000	10	40041	40041	40041	40041	40041
160024	41226	300	0	0	1	523	4576	25	160010	10	160060	10	160000	50	1320000	1	1	10	40021	41226	41226	21146	0	3	21199	160010	20	160000	20	480000	41226	41226	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	6	1	4	16	2	1	1	4	7	40037	20	9	160000	10	40042	40041	40041	40041	42028
160024	40040	300	0	0	53	67	0	63	160204	10	160001	10	160000	50	1280000	1	1	10	40021	40040	42281	22212	0	3	21206	160010	20	160000	20	480000	41226	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	5	1	4	16	2	1	1	4	3	41223	40	8	160000	10	42319	40041	42319	40041	40041
160024	40040	300	0	0	0	47	0	25	160045	10	160053	10	160000	50	1280000	1	1	10	40021	41219	40040	19996	0	3	20021	160010	20	160000	20	480000	40041	41219	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	6	1	4	16	2	1	1	4	4	40039	40	8	160000	10	41227	41227	40041	40041	40041
160024	41219	316	0	0	1	67	4576	25	160010	10	160060	10	160000	50	1280000	1	1	10	40021	40040	42318	19996	0	3	20020	160010	20	160000	20	480000	40040	42318	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	6	1	4	16	2	1	1	4	3	40037	20	8	160000	10	41227	40041	40041	41227	42282
160024	41226	299	0	0	1	47	0	25	160010	10	160000	10	160000	50	1319999	1	1	10	42299	40040	41226	19996	0	3	20020	160010	20	160000	20	480000	40041	42318	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	8	2	4	16	2	1	1	3	4	41223	20	16	160000	10	40041	41220	40041	42319	40041
160024	40042	300	0	0	60	47	0	25	160070	10	160000	10	160000	50	5728047	1	1	10	41207	40040	40040	19996	35	3	20021	160010	20	160000	20	480000	42318	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	1	10022	13	7	1	6	16	2	1	1	4	4	40037	20	8	160000	10	40041	42319	40844	40041	41230
160024	41226	300	0	0	0	73	4576	25	160070	10	160000	10	160000	50	1280000	1	1	10	42299	40040	42318	22244	0	3	20020	160010	20	160000	20	480000	40040	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	16	7	1	4	16	2	1	1	6	6	40037	20	8	160000	10	40041	40041	42319	40041	40041

FCMLA (vector, by element, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations