Firestorm: FCMLA (vector, by element, 8H) measurements

Code:

  fcmla v0.8h, v1.8h, v2.h[1], #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	12	897	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	18	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	1	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	82	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	1	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	82	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	79	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	1	3	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fcmla v0.8h, v1.8h, v2.h[1], #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	299	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38115	0	6	38741	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	1	16	0	1	39490	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	1	84	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38115	0	6	38741	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	39489	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	1	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38115	0	6	38741	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	39489	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	82	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38115	0	7	38740	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	39489	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38115	0	6	38741	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	39490	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38115	0	6	38741	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	39490	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38115	0	7	38740	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	39490	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38115	0	6	38741	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	3	1	1	1	718	0	16	0	0	39489	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	15	1	82	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38115	0	6	38741	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	39489	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38115	0	7	38740	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	39489	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	1	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39389	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	726	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fcmla v0.8h, v0.8h, v1.h[1], #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	3	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	42	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	261	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	20	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	27	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	2	0	3	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	39	441	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	351	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	33	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	420	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	6	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	15	0	943	39407	25	10010	10	10000	10	10000	50	5706908	1	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	0	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	225	0	6778	39407	25	10010	10	10000	10	10000	50	5706908	1	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	0	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	30	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	0	0	3	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	30	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	0	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	201	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	0	40018	40037	40037	38130	17	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	0	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	114	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	0	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	417	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	0	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	369	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	0	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	240	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	0	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	495	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	0	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fcmla v0.8h, v1.8h, v0.h[1], #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	39	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	747	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	205	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38122	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	411	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	299	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	5	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40158	40085	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	1	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40022	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fcmla v0.8h, v8.8h, v9.h[1], #90
  movi v1.16b, 0
  fcmla v1.8h, v8.8h, v9.h[1], #90
  movi v2.16b, 0
  fcmla v2.8h, v8.8h, v9.h[1], #90
  movi v3.16b, 0
  fcmla v3.8h, v8.8h, v9.h[1], #90
  movi v4.16b, 0
  fcmla v4.8h, v8.8h, v9.h[1], #90
  movi v5.16b, 0
  fcmla v5.8h, v8.8h, v9.h[1], #90
  movi v6.16b, 0
  fcmla v6.8h, v8.8h, v9.h[1], #90
  movi v7.16b, 0
  fcmla v7.8h, v8.8h, v9.h[1], #90

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	151	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	3	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	705	25	80100	100	80000	100	80000	500	640000	0	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10111	1	16	1	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20075	151	0	9	0	0	52	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80108	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	3	1	1	5	25	4	1	1	3	3	20049	2	20	2	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	48	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10027	3	1	1	3	34	2	1	1	3	3	20049	2	20	2	160000	10	20062	20053	20053	20053	20053
160024	20052	150	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	20033	20061	20052	3	23	80012	20	80000	20	240000	20052	20061	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10026	3	1	1	3	34	2	1	2	3	2	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	52	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	9	0	0	10026	3	1	1	3	25	2	1	1	4	2	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	51	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10026	3	1	1	3	25	2	1	1	3	3	20049	2	20	1	160000	10	20053	20137	20136	20053	20136
160024	20052	150	0	15	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10027	3	1	1	3	25	2	1	1	2	3	20049	2	20	1	160000	10	20053	20053	20053	20053	20153
160024	20052	150	0	0	0	0	46	27	80012	12	80000	12	80218	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10027	3	1	1	4	25	2	1	1	3	2	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	73	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	3	1	1	2	25	2	1	1	2	4	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	33	0	0	46	29	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20134	20144	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	3	1	2	3	25	2	2	1	3	3	20049	2	20	2	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	432	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20061	3	23	80012	20	80000	20	240000	20061	20052	1	1	160021	10	9	10	10	160000	10	9	0	0	0	0	10025	3	1	1	3	25	2	2	1	3	4	20049	2	20	1	160000	10	20053	20053	20053	20053	20053

Test 6: throughput

Count: 16

Code:

  fcmla v0.8h, v16.8h, v17.h[1], #90
  fcmla v1.8h, v16.8h, v17.h[1], #90
  fcmla v2.8h, v16.8h, v17.h[1], #90
  fcmla v3.8h, v16.8h, v17.h[1], #90
  fcmla v4.8h, v16.8h, v17.h[1], #90
  fcmla v5.8h, v16.8h, v17.h[1], #90
  fcmla v6.8h, v16.8h, v17.h[1], #90
  fcmla v7.8h, v16.8h, v17.h[1], #90
  fcmla v8.8h, v16.8h, v17.h[1], #90
  fcmla v9.8h, v16.8h, v17.h[1], #90
  fcmla v10.8h, v16.8h, v17.h[1], #90
  fcmla v11.8h, v16.8h, v17.h[1], #90
  fcmla v12.8h, v16.8h, v17.h[1], #90
  fcmla v13.8h, v16.8h, v17.h[1], #90
  fcmla v14.8h, v16.8h, v17.h[1], #90
  fcmla v15.8h, v16.8h, v17.h[1], #90

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40427	300	0	39	0	0	42	0	25	160117	100	160022	100	160000	500	5715261	41186	41190	42285	19973	0	3	19998	160100	200	160000	200	480000	41190	40043	1	1	160201	100	99	100	100	160000	100	0	15	10110	3	16	4	4	40037	160000	100	41191	42286	40041	40041	40041
160204	41209	300	0	21	0	0	82	4541	25	160100	100	160001	100	160000	500	1280000	40021	42297	41227	19973	0	3	21148	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	10110	4	16	4	3	40037	160000	100	41220	41205	40041	40041	40041
160204	40040	300	0	15	0	0	61	4485	25	160100	100	160000	100	160000	500	1280000	40021	41190	41205	22222	0	3	19998	160100	200	160000	200	480000	40040	41204	1	1	160201	100	99	100	100	160000	100	0	0	10110	4	16	4	4	40037	160000	100	40041	40044	40726	40041	42286
160204	40040	309	0	0	0	1	271	4485	25	160100	100	160000	100	160000	500	1280000	40021	42318	40040	21095	0	3	21148	160100	200	160000	200	480000	41205	41190	1	1	160201	100	99	100	100	160000	100	0	0	10110	3	16	4	4	41202	160000	100	40041	40041	40041	40041	41191
160204	40040	300	0	0	0	22	42	4485	25	160117	100	160000	100	160000	500	1280000	40021	41190	41205	19973	0	3	19998	160100	200	160000	200	480000	41190	40040	1	1	160201	100	99	100	100	160000	100	0	0	10110	4	16	4	4	40040	160000	100	40041	40041	40041	41191	40041
160204	41190	300	0	42	0	0	518	3753	43	160279	100	160102	114	160107	500	1280000	40021	40040	41190	19973	0	3	21148	160100	200	160000	200	480000	40043	40040	1	1	160201	100	99	100	100	160000	100	0	0	10110	4	16	3	4	40037	160000	100	41191	41206	41191	41206	41191
160204	41190	300	0	9	0	22	61	0	25	160100	100	160022	100	160000	500	5715261	40021	40040	40040	21095	0	3	19998	160100	200	160000	200	480000	40040	41190	1	1	160201	100	99	100	100	160000	100	0	0	10110	3	16	4	4	42282	160000	100	40044	40041	40041	41191	40041
160204	40040	300	0	75	0	22	61	0	25	160100	100	160000	100	160000	500	1319999	40021	41190	40040	19973	0	3	19998	160100	200	160000	200	480000	41190	41209	1	1	160201	100	99	100	100	160000	100	0	0	10110	4	16	3	4	40037	160000	100	40041	41206	41191	40042	40041
160204	41204	300	0	33	0	0	726	0	25	160100	100	160000	100	160000	500	1319999	40021	40040	40040	19973	0	3	21148	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	10110	4	16	4	4	41202	160000	100	40041	41191	41220	41205	40041
160204	41190	317	0	12	0	0	42	4485	25	160100	100	160000	100	160000	500	1280000	41171	40040	40040	21095	0	3	19998	160100	200	160000	200	480000	40040	41261	1	1	160201	100	99	100	100	160000	100	0	0	10110	4	16	4	4	40037	160000	100	40042	41191	42286	40041	41191

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	st unit uop (a7)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40097	306	1	0	0	0	0	35	0	47	0	25	160045	10	160053	10	160000	50	1280000	1	1	5	41200	0	41226	40040	19996	0	3	20023	160119	20	160210	20	480630	40040	40042	1	1	160021	10	9	10	10	160000	10	0	0	0	141	0	10022	8	1	1	9	16	2	1	1	11	7	41226	0	20	8	160000	10	41227	40042	40041	40041	40041
160024	40051	308	0	0	0	0	0	53	0	67	0	25	160010	10	160035	10	160000	50	1280000	0	1	5	40021	0	40040	41226	19996	0	3	22298	160010	20	160000	20	480000	40040	42318	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	4	1	7	16	2	1	1	7	15	40037	0	20	9	160000	10	40041	42319	40041	42319	40041
160024	40042	299	0	0	0	0	0	35	0	47	0	25	160010	10	160053	10	160000	50	1280000	1	1	5	40021	0	40040	42318	22244	0	3	20020	160010	20	160000	20	480000	40040	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	162	0	10022	8	4	1	15	16	2	1	1	15	7	42315	0	20	8	160000	10	42282	40041	40042	42319	40041
160024	40055	317	0	0	0	0	0	0	0	47	0	293	160501	12	160172	11	160000	61	1486934	1	1	5	41207	0	40040	40814	21141	0	10	20891	160010	20	160169	20	480624	40622	40149	2	1	160021	10	9	10	10	160000	10	4	0	0	0	0	10022	8	4	1	7	16	2	1	1	11	7	42282	1	20	9	160000	10	40807	41094	40041	41227	41313
160024	40040	303	0	1	1	1041	598	1	0	47	4607	25	160010	10	160000	10	160000	50	5728047	1	1	5	40021	0	42281	41219	19996	0	3	20020	160010	20	160000	20	480000	40040	40095	2	1	160021	10	9	10	10	160000	10	0	1	1	0	0	10022	8	4	1	11	16	2	1	1	11	11	41223	0	20	8	160000	10	41220	40041	40043	42303	42282
160024	40092	300	0	0	0	0	0	53	0	49	0	25	160045	10	160001	10	160000	50	1280000	1	1	5	40021	0	42318	40040	19996	0	3	22298	160010	20	160000	20	480000	41226	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	237	0	10022	8	4	1	11	16	4	1	1	7	15	40037	0	20	8	160000	10	40041	40043	41227	40041	40041
160024	42285	299	0	0	0	0	0	0	0	89	0	25	160010	10	160035	10	160000	50	1280000	1	1	5	40021	0	40040	41229	21146	25	3	21206	160010	20	160000	20	480000	40040	42318	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	8	4	1	11	16	2	1	1	11	11	42315	0	20	8	160000	10	40041	40041	41227	40041	40041
160024	42281	299	0	0	0	0	0	60	0	53	0	25	160010	10	160000	10	160000	50	1280000	1	1	5	41200	0	41219	40040	19996	0	3	20020	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	4	1	11	16	4	1	1	11	7	40039	0	40	9	160000	10	40041	42282	41220	41227	40041
160024	40101	300	0	0	0	0	0	0	0	53	0	25	160010	10	160035	10	160000	50	5868333	1	1	5	40021	0	41226	41226	19996	25	3	20020	160010	20	160000	20	480000	40041	41219	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	4	1	11	16	2	1	1	7	15	40037	0	20	8	160000	10	40041	42319	40041	42286	41227
160024	40102	309	0	0	0	0	0	1	0	47	0	25	160045	10	160001	10	160000	50	5728047	1	1	5	40021	0	40040	42281	19996	0	3	20020	160010	20	160000	20	480000	41226	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	33	0	10022	8	4	1	7	16	2	1	1	7	11	40037	0	20	8	160000	10	40041	40041	40041	40041	42319

FCMLA (vector, by element, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations