Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMLE (vector, zero, 2S)

Test 1: uops

Code:

  fcmle v0.2s, v0.2s, #0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715061168625100010001000264521201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
1004203715061168625100010001000264521201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
1004203715061168625100010001000264521201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371524103168625100010001000264521201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
1004203715061168625100010001000264521201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
1004203716084168625100010001000264521201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
1004203715084168625100010001000264521201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
1004203715061168625100010001000264521201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
1004203715061168625100010001000264521201820372037157131895100010001000203720371110011000373116111786100020382038203820382038
1004203715082168625100010001000264521201820372037157131895100010001000203720371110011000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  fcmle v0.2s, v0.2s, #0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000821968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011641197910100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000841968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150001471968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100640316221982210000102003820038200382003820038
1002420037150399611968625100101010000121015250284752120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
100242003715001561968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100640216231978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150270611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
100242003715001491968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  fcmle v0.2s, v8.2s, #0
  fcmle v1.2s, v8.2s, #0
  fcmle v2.2s, v8.2s, #0
  fcmle v3.2s, v8.2s, #0
  fcmle v4.2s, v8.2s, #0
  fcmle v5.2s, v8.2s, #0
  fcmle v6.2s, v8.2s, #0
  fcmle v7.2s, v8.2s, #0
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005715002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010011151184160020035800001002003920039200392003920039
802042003815002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010011151180160020035800001002003920039200392003920039
802042003815054369425801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010011151180160020035800001002003920039200392003920039
802042003815002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010011151180160020035800001002003920039200392003920039
802042003815039225801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010011151180160020035800001002003920039200392003920039
802042003815002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010011151180160020035800001002003920039200392003920039
802042003815002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010011151180163020035800001002003920039200392003920039
802042003815002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010011151180160020035800001002003920039200392003920039
802042003815002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010011151180160020035800001002003920039200392003920039
802042003815002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010011151180160020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5d60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)dbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200501500000000210258001010800001080000506400001120019200382003899963100188001020800002080000200382003811800211091010800001000000050201160112003580000102003920039200392003920039
800242003815000004920044258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000000050201160112003580000102003920039200392003920039
8002420038150000000039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000000050201160112003580000102003920039200392003920039
8002420038150000000039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000000050201160112003580000102003920039200392003920039
8002420038149000000039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000000050201160112003580000102003920039200392003920039
800242003815000005100039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000000050201160112003580000102003920039200392003920039
8002420038150000000039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000000050201160112003580000102003920039200392003920039
8002420038150000000039258001010800001080000506400000020019200382003899963100188001020800002080000200382003811800211091010800001000000050891160112003580000102003920039200392003920039
8002420038150000000039258001010800001080000506400000020019200382003899963100188001020800002080000200382003811800211091010800001000000050201160112003580000102003920039200392003920039
8002420038150000000039258001010800001080000506400000020019200382003899963100188001020800002080000200382003811800211091010800001000000050201160112003580000102003920039200392003920039