Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMLT (scalar, zero, H)

Test 1: uops

Code:

  fcmlt h0, h0, #0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150961168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150961168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500103168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500168168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150084168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037160061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  fcmlt h0, h0, #0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000661968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715009611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150001031968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010010640216221978610000102003820038200382003820038
1002420037150120611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010010640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010013640216221978610000102003820038200382003820038
1002420037150001661968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
1002420037150007491968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  fcmlt h0, h8, #0
  fcmlt h1, h8, #0
  fcmlt h2, h8, #0
  fcmlt h3, h8, #0
  fcmlt h4, h8, #0
  fcmlt h5, h8, #0
  fcmlt h6, h8, #0
  fcmlt h7, h8, #0
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003815000012425801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000001115118416200350800001002003920039200392003920039
802042003815000152925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000001115118016200350800001002003920039200392003920039
802042003815000074625801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000001115118016200350800001002003920039200392003920039
802042003815000066225801081008000810080020500640132020019200492003899776998980120200800322008003220038200381180201100991001008000010000001115118016200350800001002003920039200392003920039
8020420038150000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001005501201115118016200350800001002003920039200392003920039
802042003815000029125801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000301115118016200350800001002003920039200392003920039
80204200381500002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000001115118016200350800001002003920039200392003920039
80204200381500002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000001115118016200350800001002003920039200392009120039
80204200381500002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200921180201100991001008000010000001115118016200350800001002003920039200392003920039
802042003815000069425801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000001115118016200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500003925800101080000108000050640000020019200382003899960310018800102080000208000020038200381180021109101080000100005032116112003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899960310018800102080000208000020038200381180021109101080000100005032116122003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899960310018800102080000208000020038200381180021109101080000100005030116112003580000102003920039200392003920039
80024200381500063925800101080000108000050640000120019200382003899967310018800102080000208000020038200381180021109101080000100005030116112003580000102003920039200392003920039
800242003815000025225800101080000108000050640000120019200382003899960310018800102080000208000020038200381180021109101080000100005032316312003580000102003920039200392003920039
800242003815001012725800101080000108000050640000120019200382003899960310018800102080000208000020038200381180021109101080000100005032116112003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899960310018800102080000208000020038200381180021109101080000100005030116112003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899960310018800102080000208000020038200381180021109101080000100005030116112003580000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899960310018800102080000208000020038200381180021109101080000100005030116112003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899960310018800102080000208000020038200381180021109101080000100005030116112003580000102003920039200392003920039