Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMPE (scalar, D)

Test 1: uops

Code:

  fcmpe d0, d1
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0f5f6f7f8fd
100410388049251000100010008000101910381038864389610001000200010381038111001100007311611103310391039103910391039
100410387049251000100010008000101910381038864389610001000200010381038111001100007311611103310391039103910391039
1004103879049251000100010008000101910381038864389610001000200010381038111001100007311611103310391039103910391039
100410387049251000100010008000101910381038864389610001000200010381038111001100007311611103310391039103910391039
100410387049251000100010008000101910381038864389610001000200010381038111001100007311611103310391039103910391039
100410388049251000100010008000101910381038864389610001000200010381038111001100007311611103310391039103910391039
100410388049251000100010008000101910381038864389610001000200010381038111001100007311611103310391039103910391039
100410388049251000100010008000101910381038864389610001000200010381038111001100007311611103310391039103910391039
100410387049251000100010008000101910381038864389610001000200010381038111001100007311611103310391039103910391039
100410387072251000100010008000101910381038864389610001000200010381038111001100007311611103310391039103910391039

Test 2: Latency 3->1

Chain cycles: 2

Code:

  fcmpe d0, d1
  fcsel d0, d2, d3, eq
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

retire uop (01)cycle (02)03091e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
2020440037299000613982225201001002000010020000500285388014001840037400373731633749520100200200002005000040037400371120201100991001002000010100000001310116113990902100001004003840038400384003840038
2020440037300000613982225201001002000010020000500285388014001840037400373731633749520100200200002005000040037400371120201100991001002000010100000001310116113990900100001004003840038400384003840038
2020440037299000613982225201001002000010020000500285388014001840037400373731633749520100200200002005000040037400371120201100991001002000010100000001310116113990900100001004003840038400384003840038
20204400372990006139822252010010020000100200005002853880140018400374003737316337495201002002000020050000400374003711202011009910010020000101000000181310116113990900100001004003840038400384003840038
20204400373000006139822252010010020000100200005002853880040018400374003737316337495201002002000020050000400374003711202011009910010020000101000000121310116113990900100001004003840038400384003840038
2020440037300000613982225201001002000010020000500285388004001840037400373731633749520100200200002005000040037400371120201100991001002000010100000001310116113990900100001004003840038400384003840038
2020440037300000613982225201001002000010020000500285388014001840037400373734333751420100200200002005000040037400371120201100991001002000010100000801310116113990900100001004003840038400384003840073
2020440037300000613982225201001002000010020000500285388004001840037400373731633749520100200200002005000040037400371120201100991001002000010100000001310116113990900100001004003840038400384003840038
2020440037300000613982225201001002000010020000500285388014001840037400373731633749520100200200002005000040037400371120201100991001002000010100000001310116113990900100001004003840038400384003840038
2020440037300000613982225201001002000010020000500285388014001840037400373731633749520100200200002005000040037400371120201100991001002000010100000001310116113990900100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
2002440037300000027653982225200101020000102000050285388004001840037400373733833751720010202000020500004003740037112002110910102000010010101270316333991010000104003840038400384003840038
200244003729900104413982225200101020000102000050285388004001840037400373733833751720010202000020500004003740037112002110910102000010010001270316333991010000104003840038400384003840038
20024400373000000613982225200101020000102000050285388014001840037400373733833751720010202000020500004003740037112002110910102000010010001270416233991010000104003840038400384003840038
20024400373000000613982225200101020000102000050285388014001840037400373733833751720010202000020500004003740037112002110910102000010010001270316333991010000104003840038400384003840038
20024400372990000613982225200101020000102000050285388004001840037400373733833751720010202000020500004003740037112002110910102000010010001270316333991010000104003840038400384003840038
20024400373000000613982225200101020000102000050285388014001840037400373733833751720010202000020500004003740037112002110910102000010010001270316333991010000104003840038400384003840038
20024400373000000613982225200101020000102000050285388014001840037400373733833751720010202000020500004003740037112002110910102000010010001270316333991010000104003840038400384003840038
20024400373000000613982225200101020000102000050285388014001840037400373733833751720010202000020500004003740037112002110910102000010010001270316333991010000104003840038400384003840038
20024400373000000613982225200101020000102000050285388014001840037400373733833751720010202000020500004003740037112002110910102000010010001270316233991010000104003840038400384003840038
20024400373000000613982225200101020000102000050285388004001840037400373733833751720010202000020500004003740037112002110910102000010010001270316433991010000104003840038400384003840038

Test 3: Latency 3->2

Chain cycles: 2

Code:

  fcmpe d0, d1
  fcsel d1, d2, d3, eq
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
2020440037300061398222520100100200001002000050028538800400184003740037373163374952010020020000200500004003740037112020110099100100200001010000013101161139909100001004003840038400384003840038
2020440037300061398222520100100200001002000050028538800400184003740037373163374952010020020000200500004003740037112020110099100100200001010000013101161139909100001004003840038400384003840038
2020440037300061398222520100100200001002000050028538801400184003740037373163374952010020020000200500004003740037112020110099100100200001010000013101161139909100001004003840038400384003840038
2020440037300061398222520100100200001002000050028538800400184003740037373163374952010020020000200500004003740037112020110099100100200001010000013101161139909100001004003840038400384003840038
2020440037299061398222520100100200001002000050028538801400184003740037373163374952010020020000200500004003740037112020110099100100200001010000013101161139909100001004003840038400384003840038
2020440037300061398222520100100200001002000050028538800400184003740037373163374952010020020000200500004003740037112020110099100100200001010000013101161139909100001004003840038400384003840038
2020440037300061398222520100100200001002000050028538800400184003740037373163374952010020020000200500004003740037112020110099100100200001010000013101161139909100001004003840038400384003840038
2020440037299061398222520100100200001002000050028538801400184003740037373163374952010020020000200500004003740037112020110099100100200001010000013101161139909100001004003840038400384003840038
2020440037300061398222520100100200001002000050028538800400184003740037373163374952010020020000200500004003740037112020110099100100200001010000013101161139909100001004003840038400384003840038
20204400372990726398222520100100200001002000050028538800400184003740037373163374952010020020000200500004003740037112020110099100100200001010000013101161139909100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
2002440037300006139822252001010200001020000502853880040018400374003737338337517200102020000205000040037400371120021109101020000100100000000012703163339910010000104003840038400384003840038
2002440037300006139822252001010200001020000502853880040018400374003737338337517200102020000205000040037400371120021109101020000100100000000012703162539910010000104003840038400864003840038
2002440037299906139822252001010200001020080502855844040018400374003737338337517200102020000205000040037402261120021109101020000100100010000012703162339910010000104003840038400384003840038
2002440037300270145939822252001010200001020000502853880040018400374003737338337517200102020000205000040037400371120021109101020000100100000000012703163239910010000104003840038400384003840038
2002440037300006139822252001010200001020000502853880040126400374003737338337517200102020000205000040037400371120021109101020000100100000000012702163339910010000104003840038400384003840038
2002440037299006139822252001010200001020000502853880040018400374003737338337517200102020000205000040037400371120021109101020000100100000000012704164339910010000104003840038400384003840038
20024400373000047739822612003612200241020000502853880040018400374003737338337517200102020000205000040037400373120021109101020000100102200000012893162339943210000104003840038400384003840038
2002440037300006139822252001010200001020000502853880040018400374003737338337517200102020000205000040037400371120021109101020000100100000020013023243339910010000104003840038400384003840038
20024400373004806139822252001010200001020000502853880040018400374003737338337517200102020000205000040037400371120021109101020000100100010000012704162339910010000104003840038400384003840038
2002440037299006139822252001010200001020000502853880040018400374003737338337517200102020000205000040037400371120021109101020000100100000020012703164339910010000104003840038400384003840038

Test 4: throughput

Count: 8

Code:

  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204800385990000000001046258010010080000100800005006400000800198003880038699643699968010020080000200160000800388003811802011009910010080000100000003005110216118003501008003980039800398003980039
8020480038600000000000492580128100800001008000050064000018001980038800386996436999680100200800002001600008003880038118020110099100100800001000000090005110116118003501008003980039800398003980039
80204800386000000000004925801001008000010080000500640000180019800388003869964369996801002008000020016000080038800381180201100991001008000010000000159005110116118003501008003980039800398003980039
8020480038599000000000492580100100800001008000050064000008001980038800386996436999680100200800002001600008003880038118020110099100100800001000002012005110116118003501008003980039800398003980039
802048003860000000000049258010010080000100800005006400001800198003880038699643699968010020080000200160000800388003811802011009910010080000100000009005110116118003501008003980039800398003980039
80204800386000000000004925801001008000010080000500640000180019800388003869964369996801002008000020016000080038800381180201100991001008000010000000183005110116118003501008003980039800398003980039
802048003860000000000016025801001008000010080000500640000080019800388003869964369996801002008000020016000080038800381180201100991001008000010000000141005110116118003501008003980039800398003980039
8020480038600000000000492580100100800001008000050064000018001980038800386996436999680100200800002001600008003880038118020110099100100800001000000090005110116118003501008003980039800398003980039
8020480038599000000000492580100100800001008000050064000018001980038800386996436999680135200801512001600008003880038118020110099100100800001000000012005110116118003501008003980039800398003980039
802048003860000000000049258010010080000100800005006400001800198003880038699643699968010020080000200160000800388003811802011009910010080000100000001110151101161180035101008003980039800398003980039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)030918191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accdcfd0d5map dispatch bubble (d6)daddfetch restart (de)dfe0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800248003861500000492580010108000010800005064000008001980038800386998637001880010208000020160000800388003811800211091010800001000000810502406160234800330108003980039800398003980039
8002480038599000004925800101080000108000050640000180019800388003869986370018800102080000201600008003880038118002110910108000010000001260502404160634800330108003980039800398003980039
80024800386000001200492580010108000010800005064000008001980038800386998637001880010208000020160000800388003811800211091010800001000000990502403160565800330108003980039800398003980039
8002480038599000004802580010108000010800005064000008001980038800386998637001880010208000020160000800388003821800211091010800001000060210502405160334800330108003980039800398003980039
80024800386010000049258001010800001080000506400001800198003880038699863700188001020800002016000080038800381180021109101080000100000030502502160654800330108003980039800398003980039
8002480038600000001146258001010800001080000506400000800198003880038699863700188001020800002016000080038800381180021109101080000100000090502406160334800330108003980039800398003980039
800248003860000000772580010108000010800005064000018001980038800386998637001880010208000020160000800388003811800211091010800001000030810502402160324800330108003980039800398003980039
8002480038600000004925800101080000108000050640000180019800388003869986370018800102080000201600008003880038118002110910108000010000001681502403160565800330108003980039800398003980039
8002480038621000004925800101080000108000050640000080019800388003869986370018800102080000201600008003880038118002110910108000010000001140502606160324800330108003980039800398003980039
8002480038601000004925800101080000108000050640000080019800388003869986370018800102080000201600008003880038118002110910108000010000001470502505160334800330108003980039800398003980039