Firestorm: FCMPE (scalar, D) measurements

Code:

  fcmpe d0, d1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	1038	8	0	49	25	1000	1000	1000	8000	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	7	0	49	25	1000	1000	1000	8000	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	7	90	49	25	1000	1000	1000	8000	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	7	0	49	25	1000	1000	1000	8000	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	7	0	49	25	1000	1000	1000	8000	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	8	0	49	25	1000	1000	1000	8000	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	8	0	49	25	1000	1000	1000	8000	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	8	0	49	25	1000	1000	1000	8000	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	7	0	49	25	1000	1000	1000	8000	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	7	0	72	25	1000	1000	1000	8000	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039

Test 2: Latency 3->1

Chain cycles: 2

Code:

  fcmpe d0, d1
  fcsel d0, d2, d3, eq

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	299	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	0	0	1310	1	16	1	1	39909	0	2	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	0	0	1310	1	16	1	1	39909	0	0	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	0	0	1310	1	16	1	1	39909	0	0	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	0	18	1310	1	16	1	1	39909	0	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	0	12	1310	1	16	1	1	39909	0	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	0	0	1310	1	16	1	1	39909	0	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37343	3	37514	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	8	0	1310	1	16	1	1	39909	0	0	10000	100	40038	40038	40038	40038	40073
20204	40037	300	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	0	0	1310	1	16	1	1	39909	0	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	0	0	1310	1	16	1	1	39909	0	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	0	0	1310	1	16	1	1	39909	0	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	0	0	0	2765	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	1	0	1270	3	16	3	3	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	1	0	441	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	1270	3	16	3	3	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	1270	4	16	2	3	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	1270	3	16	3	3	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	1270	3	16	3	3	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	1270	3	16	3	3	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	1270	3	16	3	3	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	1270	3	16	3	3	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	1270	3	16	2	3	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	1270	3	16	4	3	39910	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 3->2

Chain cycles: 2

Code:

  fcmpe d0, d1
  fcsel d1, d2, d3, eq

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	726	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	0	0	0	0	1270	3	16	3	3	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	0	0	0	0	1270	3	16	2	5	39910	0	10000	10	40038	40038	40086	40038	40038
20024	40037	299	9	0	61	39822	25	20010	10	20000	10	20080	50	2855844	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40226	1	1	20021	10	9	10	10	20000	10010	0	0	1	0	0	0	0	0	1270	3	16	2	3	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	27	0	1459	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	0	0	0	0	1270	3	16	3	2	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40126	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	0	0	0	0	1270	2	16	3	3	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	0	0	0	0	1270	4	16	4	3	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	477	39822	61	20036	12	20024	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	3	1	20021	10	9	10	10	20000	10010	2	2	0	0	0	0	0	0	1289	3	16	2	3	39943	2	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	0	2	0	0	1302	3	24	3	3	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	48	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	1	0	0	0	0	0	1270	4	16	2	3	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	0	2	0	0	1270	3	16	4	3	39910	0	10000	10	40038	40038	40038	40038	40038

Test 4: throughput

Count: 8

Code:

  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80038	599	0	0	0	0	0	0	0	0	0	1046	25	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	3	0	0	5110	2	16	1	1	80035	0	100	80039	80039	80039	80039	80039
80204	80038	600	0	0	0	0	0	0	0	0	0	49	25	80128	100	80000	100	80000	500	640000	1	80019	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	90	0	0	5110	1	16	1	1	80035	0	100	80039	80039	80039	80039	80039
80204	80038	600	0	0	0	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	159	0	0	5110	1	16	1	1	80035	0	100	80039	80039	80039	80039	80039
80204	80038	599	0	0	0	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	2	0	12	0	0	5110	1	16	1	1	80035	0	100	80039	80039	80039	80039	80039
80204	80038	600	0	0	0	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	9	0	0	5110	1	16	1	1	80035	0	100	80039	80039	80039	80039	80039
80204	80038	600	0	0	0	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	183	0	0	5110	1	16	1	1	80035	0	100	80039	80039	80039	80039	80039
80204	80038	600	0	0	0	0	0	0	0	0	0	160	25	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	141	0	0	5110	1	16	1	1	80035	0	100	80039	80039	80039	80039	80039
80204	80038	600	0	0	0	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	90	0	0	5110	1	16	1	1	80035	0	100	80039	80039	80039	80039	80039
80204	80038	599	0	0	0	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	69964	3	69996	80135	200	80151	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	12	0	0	5110	1	16	1	1	80035	0	100	80039	80039	80039	80039	80039
80204	80038	600	0	0	0	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	111	0	1	5110	1	16	1	1	80035	10	100	80039	80039	80039	80039	80039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cd	cf	d0	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	df	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80038	615	0	0	0	0	0	49	25	80010	10	80000	10	80000	50	640000	0	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	81	0	5024	0	6	16	0	2	3	4	80033	0	10	80039	80039	80039	80039	80039
80024	80038	599	0	0	0	0	0	49	25	80010	10	80000	10	80000	50	640000	1	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	126	0	5024	0	4	16	0	6	3	4	80033	0	10	80039	80039	80039	80039	80039
80024	80038	600	0	0	0	120	0	49	25	80010	10	80000	10	80000	50	640000	0	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	99	0	5024	0	3	16	0	5	6	5	80033	0	10	80039	80039	80039	80039	80039
80024	80038	599	0	0	0	0	0	480	25	80010	10	80000	10	80000	50	640000	0	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	2	1	80021	10	9	10	10	80000	10	0	0	0	6	0	21	0	5024	0	5	16	0	3	3	4	80033	0	10	80039	80039	80039	80039	80039
80024	80038	601	0	0	0	0	0	49	25	80010	10	80000	10	80000	50	640000	1	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	3	0	5025	0	2	16	0	6	5	4	80033	0	10	80039	80039	80039	80039	80039
80024	80038	600	0	0	0	0	0	1146	25	80010	10	80000	10	80000	50	640000	0	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	9	0	5024	0	6	16	0	3	3	4	80033	0	10	80039	80039	80039	80039	80039
80024	80038	600	0	0	0	0	0	77	25	80010	10	80000	10	80000	50	640000	1	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	3	0	81	0	5024	0	2	16	0	3	2	4	80033	0	10	80039	80039	80039	80039	80039
80024	80038	600	0	0	0	0	0	49	25	80010	10	80000	10	80000	50	640000	1	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	168	1	5024	0	3	16	0	5	6	5	80033	0	10	80039	80039	80039	80039	80039
80024	80038	621	0	0	0	0	0	49	25	80010	10	80000	10	80000	50	640000	0	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	114	0	5026	0	6	16	0	3	2	4	80033	0	10	80039	80039	80039	80039	80039
80024	80038	601	0	0	0	0	0	49	25	80010	10	80000	10	80000	50	640000	0	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	147	0	5025	0	5	16	0	3	3	4	80033	0	10	80039	80039	80039	80039	80039

FCMPE (scalar, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations