Firestorm: FCMPE (scalar, S) measurements

Code:

  fcmpe s0, s1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	1038	7	0	0	49	25	1000	1000	1000	8000	0	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	8	0	0	49	25	1000	1000	1000	8000	0	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	7	0	0	49	25	1000	1000	1000	8000	0	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	8	0	0	49	25	1000	1000	1000	8000	0	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	8	0	0	49	25	1000	1000	1000	8000	0	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	8	0	0	49	25	1000	1000	1000	8000	0	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	8	0	0	49	25	1000	1000	1000	8000	0	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	7	120	0	49	25	1000	1000	1000	8000	0	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	8	0	0	49	25	1000	1000	1000	8000	0	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039
1004	1038	8	0	0	49	25	1000	1000	1000	8000	0	1019	1038	1038	864	3	896	1000	1000	2000	1038	1038	1	1	1001	1000	0	0	73	1	16	1	1	1033	1039	1039	1039	1039	1039

Test 2: Latency 3->1

Chain cycles: 2

Code:

  fcmpe s0, s1
  fcsel d0, d2, d3, eq

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	300	0	0	1641	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	0	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	0	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	0	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	0	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40228	37316	0	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20205	40037	299	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	0	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	0	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	0	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	0	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	99	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40224	37316	0	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	1310	1	16	1	1	39909	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	10	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	0	0	1270	10	10	2	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	10	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	0	0	1270	10	5	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	94	39822	25	20010	10	20000	10	20000	50	2853880	1	10	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	0	0	1270	10	5	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	61	39822	42	20010	10	20000	10	20000	50	2853880	1	10	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	0	0	1270	10	5	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	0	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	0	0	1270	0	0	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	10	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	0	0	1270	0	0	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	10	40018	0	40037	40037	37338	3	37517	20010	20	20107	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	0	0	1270	0	0	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	0	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	0	0	1270	0	0	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	10	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	0	0	1270	0	0	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	10	40018	0	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	0	0	1270	0	0	1	16	1	1	39910	0	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 3->2

Chain cycles: 2

Code:

  fcmpe s0, s1
  fcsel d1, d2, d3, eq

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	0	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40074	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20116	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	1	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40073
20204	40037	300	0	61	39822	25	20100	100	20000	100	20000	500	2853880	1	40018	40037	40037	37316	3	37495	20100	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	100	20000	10100	0	0	0	1310	1	16	1	1	39909	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	3725	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	61	39822	25	20010	10	20000	10	20000	50	2853880	1	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	22	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	84	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	3	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	1270	1	16	1	1	39910	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	61	39822	25	20010	10	20000	10	20000	50	2853880	0	40018	40037	40037	37338	3	37517	20010	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	10	20000	10010	0	0	0	0	1270	2	16	1	1	39910	10000	10	40038	40038	40038	40038	40038

Test 4: throughput

Count: 8

Code:

  fcmpe s0, s1
  fcmpe s0, s1
  fcmpe s0, s1
  fcmpe s0, s1
  fcmpe s0, s1
  fcmpe s0, s1
  fcmpe s0, s1
  fcmpe s0, s1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80038	599	0	0	0	0	0	0	0	0	714	25	80100	100	80000	100	80000	500	640000	0	80019	0	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	2	0	0	0	5110	2	16	1	1	80035	0	100	80039	80039	80039	80039	80039
80204	80038	600	0	0	0	0	0	0	0	0	529	25	80100	100	80000	100	80000	500	640000	0	80019	0	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80035	0	100	81447	81150	81444	81442	81573
80204	81439	608	2	0	0	0	27	27	3573	2464	5303	370	80793	128	80621	128	80725	637	644290	0	81092	0	81485	81007	70591	129	71104	80797	201	80731	202	161572	81536	81535	23	1	80201	100	99	100	100	80000	100	0	1	2	16615	4	5524	6	185	3	3	81255	31	100	81153	81630	81684	81438	81200
80204	81721	611	0	0	2	0	35	32	4707	2904	932	25	80100	100	80000	100	80000	535	640000	0	80019	0	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80035	0	100	80039	80039	80039	80039	80039
80204	80038	600	0	0	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	0	80019	0	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80035	0	100	80039	80039	80039	80039	80039
80204	80038	599	0	0	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	0	80019	0	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80035	0	100	80039	80039	80039	80039	80039
80204	80038	599	0	0	0	0	0	0	0	0	49	134	80159	124	80069	111	80175	500	640390	1	80056	0	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80035	0	100	80039	80039	80039	80039	80039
80204	80038	599	0	0	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	0	80019	0	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80035	0	100	80039	80039	80039	80039	80039
80204	80038	599	0	1	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	1	80019	0	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80035	0	100	80039	80039	80039	80039	80039
80204	80038	621	0	0	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	0	80019	0	80038	80038	69964	3	69996	80100	200	80000	200	160000	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80035	0	100	80039	80039	80039	80039	80039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	eb	? int retires (ef)	f5	f6	f7	f8	fd
80024	80038	600	0	0	0	114	25	80010	10	80000	10	80000	50	640000	0	80056	80038	80038	70028	3	70018	80010	20	80000	20	160000	80086	80086	1	1	80021	10	9	10	10	80000	10	0	0	0	2	0	5076	4	41	0	0	0	3	5	80033	0	10	80039	80039	80039	80039	80039
80024	80038	599	0	0	0	49	25	80010	10	80000	10	80050	50	640000	0	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	2	0	0	0	5020	5	16	0	0	0	3	5	80033	0	10	80039	80039	80039	80039	80039
80024	80038	620	0	9	0	714	25	80010	10	80000	10	80000	50	640000	1	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5059	5	16	0	0	0	3	5	80033	0	10	80039	80039	80039	80039	80039
80024	80038	600	0	12	0	49	25	80010	10	80000	10	80000	50	640000	1	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	1	3	0	0	5020	5	16	0	0	0	5	5	80033	0	10	80039	80039	80039	80039	80039
80024	80038	600	0	0	0	179	25	80010	10	80000	10	80000	50	640000	1	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	3	16	0	0	0	5	3	80033	0	10	80039	80039	80039	80039	80039
80024	80038	600	0	0	0	714	25	80010	10	80000	10	80000	50	640000	0	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	5	16	0	0	0	4	5	80033	0	10	80039	80039	80039	80039	80039
80024	80038	599	0	0	0	49	25	80010	10	80000	10	80000	50	640000	1	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	2	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	7	16	0	0	5	7	3	80033	0	10	80039	80039	80039	80039	80039
80024	80038	599	0	291	88	49	25	80010	10	80000	10	80000	50	640000	1	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	1	0	0	0	5020	5	16	0	0	0	5	5	80033	0	10	80039	80039	80039	80039	80039
80024	80038	600	0	0	0	49	25	80010	10	80000	10	80000	50	640000	1	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	5	16	0	0	0	3	5	80033	0	10	80039	80039	80039	80039	80039
80024	80038	644	0	0	0	181	25	80010	10	80000	10	80000	50	640000	1	80019	80038	80038	69986	3	70018	80010	20	80000	20	160000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	5	16	0	0	0	5	5	80033	0	10	80039	80039	80039	80039	80039

FCMPE (scalar, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations