Firestorm: FCSEL (scalar, D) measurements

Code:

  fcsel d0, d0, d1, lt

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	61	19822	25	10100	100	10000	100	10000	500	1423880	0	20018	20037	20037	18566	20	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	0	0	710	1	16	1	1	19907	10000	100	20038	20038	20133	20038	20038
10204	20037	150	0	0	0	61	19822	25	10100	100	10000	100	10000	500	1423880	0	20018	20037	20037	18577	3	18745	10100	200	10000	200	30285	20037	20037	1	1	10201	100	99	100	100	10000	10100	4	1	0	0	710	1	16	1	1	19907	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19822	25	10119	100	10000	112	10080	500	1423880	0	20018	20037	20133	18566	3	18745	10100	202	10000	202	30000	20037	20131	1	1	10201	100	99	100	100	10000	10100	0	0	0	0	710	1	16	1	1	19907	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	82	19822	25	10100	100	10000	100	10000	500	1423880	0	20018	20037	20037	18566	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	0	0	710	1	16	1	1	19907	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19822	25	10100	100	10000	100	10000	500	1423880	0	20018	20037	20037	18566	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	0	0	710	1	16	1	1	19907	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19822	25	10100	100	10000	100	10000	500	1423880	0	20018	20037	20037	18566	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	1313	0	710	1	16	1	1	19907	10000	100	20086	20085	20038	20038	20038
10204	20037	150	1	0	0	61	19822	25	10100	100	10000	100	10000	500	1423880	0	20018	20037	20037	18566	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	3	0	710	1	16	1	1	19907	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	12	61	19822	25	10100	100	10000	100	10000	500	1423880	1	20018	20037	20037	18566	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	0	0	710	1	16	1	1	19907	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19822	25	10100	100	10000	100	10000	500	1423880	0	20018	20037	20037	18566	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	0	0	710	1	16	1	1	19907	10000	100	20038	20038	20038	20038	20038
10204	20179	150	0	0	0	82	19822	25	10100	100	10000	100	10000	500	1423880	0	20018	20037	20037	18566	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	0	0	710	1	16	1	1	19907	10000	100	20071	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	61	19822	25	10010	10	10000	10	10000	50	1423880	0	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	640	2	16	2	2	19907	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19822	25	10010	10	10000	10	10000	50	1423880	0	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	640	2	16	2	2	19907	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19822	25	10010	10	10000	10	10000	50	1423880	0	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	640	2	16	2	2	19907	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19822	25	10010	10	10000	10	10000	50	1423880	0	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	640	2	16	2	2	19907	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19822	25	10010	10	10000	10	10000	50	1423880	1	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	640	2	16	2	2	19907	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19822	25	10010	10	10000	10	10000	50	1423880	0	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	640	2	16	2	2	19907	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	147	19822	25	10010	10	10000	10	10000	50	1423880	0	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	640	2	16	2	2	19907	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19822	25	10010	10	10000	10	10000	50	1423880	0	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	640	2	16	2	2	19907	0	10000	10	20038	20038	20038	20038	20070
10024	20037	150	0	61	19822	25	10010	10	10000	10	10000	50	1423880	0	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	642	2	16	2	2	19907	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19822	25	10010	10	10000	10	10000	50	1423880	0	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	222	640	2	16	2	2	19907	0	10000	10	20038	20038	20038	20038	20038

Test 2: uops

Code:

  fcsel d0, d1, d0, lt

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	9f	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	61	1822	25	1007	1000	1000	136880	1	2018	2037	2037	1716	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	63	0	73	2	16	2	2	1907	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1822	25	1000	1000	1000	136880	1	2018	2037	2037	1716	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	0	0	73	2	16	2	2	1907	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1822	25	1000	1012	1000	136880	1	2018	2037	2037	1716	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	0	0	73	5	16	2	2	1907	1000	2038	2038	2038	2038	2038
1004	2037	15	132	82	1822	25	1012	1000	1080	136880	1	2018	2084	2037	1716	3	1895	1000	1000	3000	2037	2037	2	1	1001	1000	1000	0	1	1	3	1008	2	73	2	16	2	2	1907	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1822	25	1000	1000	1000	136880	1	2018	2037	2037	1716	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	0	0	73	2	16	2	2	1907	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1822	25	1000	1000	1000	136880	1	2018	2037	2037	1716	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	0	0	73	2	16	2	2	1907	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1822	25	1000	1000	1000	136880	0	2018	2037	2037	1716	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	0	0	73	2	16	2	2	1961	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1822	25	1000	1000	1000	136880	1	2018	2037	2037	1716	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	0	0	73	2	16	2	2	1907	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1822	25	1000	1000	1000	136880	1	2018	2037	2037	1716	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	0	0	73	2	16	2	2	1907	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1822	25	1000	1000	1000	136880	1	2018	2037	2037	1716	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1000	0	0	0	0	0	0	73	2	16	2	2	1907	1000	2038	2038	2038	2038	2038

Test 3: Latency 1->3

Code:

  fcsel d0, d1, d0, lt

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	39	103	19822	25	10100	100	10000	100	10000	500	1423880	20018	20037	20037	18566	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	0	0	0	0	710	1	16	1	1	19907	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	61	19822	25	10100	100	10000	100	10000	500	1423880	20018	20037	20037	18566	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	0	0	0	0	710	1	16	1	1	19907	0	10000	100	20038	20038	20180	20038	20038
10204	20037	149	0	0	0	0	0	1066	19822	25	10100	100	10000	100	10000	500	1423880	20018	20037	20037	18566	3	18745	10100	200	10000	200	31143	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	0	0	0	0	710	1	16	1	1	19907	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	1	0	61	19822	25	10100	100	10000	100	10000	500	1423880	20018	20037	20037	18566	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	0	0	0	0	710	1	16	1	1	19907	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	441	19822	25	10100	100	10000	100	10000	500	1423880	20018	20037	20037	18566	3	18745	10100	200	10000	202	30000	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	0	0	0	0	710	1	16	1	1	19907	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	61	19786	25	10100	100	10000	100	10000	500	1423880	20018	20037	20037	18566	3	18745	10100	202	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	0	0	0	0	710	1	16	1	3	19907	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	61	19822	25	10100	100	10012	100	10000	500	1423880	20018	20037	20037	18566	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	0	1	3	0	710	1	16	1	1	19907	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	61	19822	25	10100	100	10000	125	10000	500	1423880	20018	20037	20037	18566	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	0	0	6	0	710	1	16	1	1	19907	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	18	61	19822	25	10100	100	10000	100	10000	616	1423880	20018	20037	20037	18566	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	0	0	0	0	710	1	16	1	1	19907	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	61	19822	25	10100	122	10000	100	10000	500	1423880	20018	20037	20037	18566	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	10100	0	0	0	0	0	0	710	2	16	1	1	19907	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	61	19822	25	10010	10	10000	10	10000	50	1423880	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	0	0	0	0	640	4	16	3	3	19907	10000	10	20038	20038	20133	20086	20038
10024	20037	150	0	0	0	0	61	19822	25	10010	10	10000	10	10000	50	1423880	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	0	0	0	0	640	3	16	3	3	19907	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19822	25	10010	10	10000	10	10000	50	1423880	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	0	0	0	0	640	3	16	3	3	19907	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	346	19822	25	10010	10	10000	10	10000	50	1423880	20018	20037	20083	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	0	0	0	0	640	3	16	3	3	19907	10000	10	20038	20038	20038	20038	20085
10024	20037	149	0	0	0	0	61	19822	25	10010	10	10000	10	10000	50	1423880	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	0	0	0	0	640	3	16	3	3	19907	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19822	25	10010	10	10000	10	10000	50	1423880	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	0	0	0	0	640	3	16	3	3	19907	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19822	25	10010	10	10000	10	10000	50	1423880	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	0	0	0	0	640	3	16	3	3	19907	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19822	25	10010	10	10000	10	10000	50	1423880	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	0	0	0	0	640	3	16	3	3	19907	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19822	25	10010	10	10000	10	10000	50	1423880	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	0	0	0	0	640	3	16	3	3	19992	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19822	25	10010	10	10000	10	10000	50	1423880	20018	20037	20037	18588	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10010	0	0	1	0	0	640	3	16	3	3	19907	10000	10	20038	20038	20038	20038	20038

Test 4: Latency 1->4

Chain cycles: 2

Code:

  fcsel d0, d1, d2, lt
  fcmp d0, d3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	inst simd alu (9a)	9f	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	299	0	61	39822	25	20200	200	20000	200	20000	1100	2853880	0	40018	40037	40037	37324	7	37490	20200	200	20008	200	50020	40037	40037	1	1	20201	100	99	100	20000	10000	0	1	1	1	1317	0	16	0	0	39918	100	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20200	200	20000	200	20000	1100	2853880	0	40018	40037	40037	37324	6	37491	20200	200	20008	200	50020	40037	40037	1	1	20201	100	99	100	20000	10000	0	1	1	1	1318	0	16	0	0	39918	100	10000	100	40038	40038	40038	40038	40038
20204	40037	299	9	726	39822	25	20200	200	20000	200	20000	1100	2853880	0	40018	40037	40037	37324	6	37491	20200	200	20008	200	50020	40037	40037	1	1	20201	100	99	100	20000	10000	0	1	1	1	1318	0	16	0	0	39919	100	10000	100	40038	40038	40038	40038	40038
20204	40037	300	132	61	39822	25	20200	200	20000	200	20000	1100	2853880	1	40018	40037	40037	37324	6	37491	20200	200	20008	200	50020	40037	40037	1	1	20201	100	99	100	20000	10000	0	1	1	1	1317	0	16	0	0	39918	100	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	61	39822	25	20200	200	20000	200	20000	1100	2853880	0	40018	40037	40037	37324	7	37491	20200	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	20000	10000	0	0	0	0	1310	1	16	1	1	39909	100	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20200	200	20000	200	20000	1100	2853880	0	40018	40037	40037	37316	3	37495	20200	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	20000	10000	0	0	0	0	1310	1	16	1	1	39909	100	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	81	39822	25	20200	200	20000	200	20000	1100	2853880	0	40018	40037	40037	37316	12	37495	20200	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	20000	10000	0	0	0	0	1310	1	16	1	1	39909	100	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	61	39822	25	20200	200	20000	200	20000	1100	2853880	0	40018	40037	40037	37316	3	37495	20200	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	20000	10000	0	0	0	0	1310	1	16	1	1	39909	100	10000	100	40038	40038	40038	40038	40038
20204	40037	300	0	536	39822	25	20200	200	20000	200	20000	1100	2853880	1	40018	40037	40037	37316	3	37495	20200	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	20000	10000	0	0	0	0	1310	1	16	1	1	39909	100	10000	100	40038	40038	40038	40038	40038
20204	40037	299	0	61	39822	25	20200	200	20000	200	20000	1100	2853880	0	40018	40037	40037	37316	3	37495	20200	200	20000	200	50000	40037	40037	1	1	20201	100	99	100	20000	10000	0	0	0	0	1310	1	16	1	1	39909	100	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	0	0	0	61	39822	25	20020	20	20000	20	20000	110	2853880	1	40018	40037	40037	37338	3	37517	20020	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	20000	10000	0	156	1270	3	16	4	3	39909	10	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	61	39822	25	20020	20	20000	20	20000	110	2853880	1	40018	40037	40037	37338	3	37517	20020	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	20000	10000	0	105	1270	3	16	3	3	39909	10	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	9	0	0	82	39822	44	20020	20	20000	20	20000	110	2853880	1	40018	40037	40037	37348	3	37517	20020	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	20000	10000	0	21	1270	2	16	3	3	39909	10	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	61	39822	25	20020	20	20000	20	20000	110	2853880	1	40018	40037	40037	37338	3	37517	20020	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	20000	10000	0	126	1270	3	16	3	2	39909	10	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	61	39822	25	20020	20	20000	20	20000	110	2854368	1	40018	40037	40037	37338	3	37517	20020	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	20000	10000	0	150	1270	3	16	4	3	39909	10	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	61	39822	25	20020	20	20000	20	20000	110	2853880	1	40018	40037	40037	37338	3	37517	20020	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	20000	10000	0	144	1270	3	16	3	4	39909	10	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	61	39822	25	20020	20	20000	20	20000	110	2853880	1	40018	40037	40037	37338	3	37517	20020	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	20000	10000	0	144	1270	3	16	3	4	39909	10	10000	10	40038	40038	40038	40038	40069
20024	40037	299	0	0	0	0	61	39822	25	20020	20	20000	20	20000	110	2853880	1	40018	40037	40085	37338	3	37517	20020	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	20000	10000	0	156	1270	3	16	3	4	39909	10	10000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	61	39822	25	20020	20	20000	20	20000	110	2853880	1	40018	40037	40037	37338	3	37517	20020	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	20000	10000	0	114	1270	3	16	3	3	39909	10	10000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	61	39822	25	20020	20	20000	20	20000	110	2853880	1	40018	40037	40037	37338	3	37517	20020	20	20000	20	50000	40037	40037	1	1	20021	10	9	10	20000	10000	0	15	1270	3	16	3	3	39909	10	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  fcsel d0, d8, d9, lt
  fcsel d1, d8, d9, lt
  fcsel d2, d8, d9, lt
  fcsel d3, d8, d9, lt
  fcsel d4, d8, d9, lt
  fcsel d5, d8, d9, lt
  fcsel d6, d8, d9, lt
  fcsel d7, d8, d9, lt

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40051	300	0	43	25	80100	100	80000	100	80000	500	640000	40019	40038	40038	29970	3	29996	80100	200	80000	200	240000	40038	40038	1	1	80201	100	99	100	100	80000	80100	0	0	0	5110	2	16	1	1	40035	0	80000	100	40039	40039	40039	40039	40039
80204	40038	300	0	43	25	80100	100	80000	100	80000	500	640000	40019	40038	40038	29970	3	29996	80100	200	80000	200	240000	40038	40038	1	1	80201	100	99	100	100	80000	80100	0	0	0	5110	1	16	1	1	40035	0	80000	100	40039	40039	40039	40039	40039
80204	40038	300	0	43	25	80100	100	80000	100	80000	500	640000	40019	40038	40038	29970	3	29996	80100	200	80000	200	240000	40038	40038	1	1	80201	100	99	100	100	80000	80100	0	0	0	5110	1	16	1	1	40035	0	80000	100	40039	40039	40039	40039	40039
80204	40038	300	0	43	25	80100	100	80000	100	80000	500	640000	40019	40038	40038	29970	3	29996	80100	200	80000	200	240000	40038	40038	1	1	80201	100	99	100	100	80000	80100	4	0	0	5110	1	16	1	1	40035	0	80000	100	40039	40039	40039	40039	40039
80204	40038	300	0	43	25	80100	100	80000	100	80000	500	640000	40019	40038	40038	29970	3	29996	80100	200	80000	200	240000	40038	40038	1	1	80201	100	99	100	100	80000	80100	0	0	0	5110	1	16	1	1	40035	0	80000	100	40039	40039	40039	40039	40039
80204	40038	300	0	43	25	80100	100	80000	100	80000	500	640000	40019	40038	40038	29970	3	29996	80100	200	80000	200	240000	40038	40038	1	1	80201	100	99	100	100	80000	80100	0	0	0	5110	1	16	1	1	40035	0	80000	100	40039	40039	40039	40039	40039
80204	40038	300	0	708	25	80100	100	80000	100	80000	500	640000	40019	40038	40038	29970	3	29996	80100	200	80000	200	240000	40038	40038	1	1	80201	100	99	100	100	80000	80100	0	0	0	5110	1	16	1	1	40035	0	80000	100	40039	40039	40039	40039	40039
80204	40038	299	0	43	25	80100	100	80000	100	80000	500	640000	40019	40038	40038	29970	3	30014	80100	200	80000	200	240000	40038	40038	1	1	80201	100	99	100	100	80000	80100	0	0	0	5110	2	16	1	1	40035	0	80000	100	40039	40039	40039	40039	40039
80204	40038	300	0	43	25	80100	100	80000	100	80000	500	640000	40019	40038	40038	29970	15	29990	80100	200	80000	200	240000	40038	40038	1	1	80201	100	99	100	100	80000	80100	5	0	0	5110	1	16	1	1	40035	0	80000	100	40039	40039	40039	40039	40039
80204	40038	300	0	43	25	80100	100	80000	100	80000	500	640000	40019	40038	40038	29970	3	29996	80100	200	80000	200	240000	40038	40038	1	1	80201	100	99	100	100	80000	80100	0	0	0	5110	1	16	1	1	40035	0	80000	100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	09	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	40044	299	0	0	0	0	708	25	80010	10	80000	10	80000	50	640000	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	240000	40038	40038	1	1	80021	10	9	10	10	80000	80010	2	0	0	5021	1	9	16	17	14	40035	80000	10	40039	40088	40088	40039	40039
80024	40038	299	1	1	0	104	89	25	80010	10	80000	10	80000	50	640000	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	240000	40038	40038	1	1	80021	10	9	10	10	80000	80010	0	0	0	5021	1	16	16	17	9	40035	80000	10	40039	40039	40039	40039	40039
80024	40038	300	1	1	0	0	89	98	80057	10	80000	10	80000	50	640000	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	240000	40038	40038	1	1	80021	10	9	10	10	80000	80010	0	3	0	5021	1	17	16	13	17	40035	80000	10	40039	40039	40039	40039	40039
80024	40038	300	1	1	0	0	89	25	80010	10	80000	10	80000	50	640000	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	240699	40038	40038	1	1	80021	10	9	10	10	80000	80010	0	0	0	5021	1	16	16	18	11	40035	80000	10	40039	40039	40039	40039	40039
80024	40038	300	1	1	0	0	89	25	80010	10	80048	10	80000	50	640000	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	240000	40038	40038	1	1	80021	10	9	10	10	80000	80010	0	0	0	5021	1	17	16	16	17	40035	80000	10	40039	40039	40039	40039	40039
80024	40038	300	1	1	0	0	376	25	80010	10	80000	10	80000	50	640000	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	240000	40038	40038	1	1	80021	10	9	10	10	80000	80010	4	0	0	5021	1	12	16	19	16	40035	80000	10	40039	40039	40039	40039	40039
80024	40038	300	1	1	0	0	89	25	80010	10	80000	10	80000	50	640000	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	240000	40038	40038	1	1	80021	10	9	10	10	80000	80010	0	0	0	5021	1	17	16	14	18	40035	80000	10	40039	40039	40039	40039	40039
80024	40038	300	1	1	0	0	89	25	80010	13	80000	10	80050	50	640000	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	240000	40038	40038	1	1	80021	10	9	10	10	80000	80010	1	0	0	5021	1	17	16	14	17	40035	80000	10	40039	40039	40039	40039	40039
80024	40038	300	1	1	0	0	89	25	80010	10	80000	10	80000	50	640000	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	240000	40038	40038	1	1	80021	10	9	10	10	80000	80010	0	0	0	5021	1	17	16	17	17	40035	80000	10	40039	40039	40039	40039	40039
80024	40038	300	1	1	0	0	89	25	80010	10	80000	10	80000	50	640000	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	240000	40038	40038	1	1	80021	10	9	10	10	80000	80010	0	0	0	5021	1	9	16	17	14	40035	80000	10	40039	40039	40039	40039	40039

FCSEL (scalar, D)

Test 1: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 2: uops

1000 unrolls and 1 iteration

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations