Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCSEL (scalar, H)

Test 1: Latency 1->2

Code:

  fcsel h0, h0, h1, lt
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715006119822251010010010000100100005001423880120018200372003718573618741101002001000820030024200372003711102011009910010010000101000011171701600199180100001002003820038200382003820038
102042003715006119822251010010010000100100005001423880120018200372003718573618741101002001000820030024200372003711102011009910010010000101000011171701600199170100001002003820038200382003820038
102042003715006119822251010010010000100100005001423880120018200372003718566318745101002001000020030000200372003711102011009910010010000101000000076411611199070100001002003820038200382003820038
1020420037150610319822251010010010000100100005001423880120090200372003718566318745101002001000020030000200372003711102011009910010010000101000000071011611199070100001002003820038200382003820038
102042003715006119822251010010010000100100005001423880120018200372003718566318745101002001000020030000200372003711102011009910010010000101000000071011611199070100001002003820038200382003820038
102042003714906119822251010010010000100100005001423880120018200372003718566318745101002001000020030000200372003711102011009910010010000101000000071011611199070100001002003820038200382003820038
102042003715006119822251010010010000100100005001423880120018200372003718566318745101002001000020030000200372003711102011009910010010000101000000071011611199070100001002003820038200382003820038
102042003715006119822251010010010000100100005001423880120018200372003718566318745101002001000020430000200372003711102011009910010010000101001127300071011611199070100001002003820038200382003820038
102042003715006119822251010010010000100100005001423880120018200712003718566318745101002001000020030000200372003711102011009910010010000101000000071011612199070100001002003820038200382003820038
1020420037150097419822251010010010000100100005001423880120018200372003718566318745101002001000020030000200372003711102011009910010010000101001000071011611199070100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000000010319822251001010100001010000501423880120018200372003718588318767100102010000203000020037200371110021109101010000100100000006404162219907010000102003820038200382003820038
10024200371500000006119822251001010100001010000501423880120018200372003718588318767100102010000203000020037200371110021109101010000100100000006403164319907010000102003820038200382003820038
10024200371500000006119822251001010100001010000501423880120018200372003718588318767100102010000203000020037200371110021109101010000100100000006404166419907010000102003820038200382003820038
10024200371500100006119822251001010100001010000501423880120018200372003718588318767100102010000203000020037200371110021109101010000100100000006403164419907010000102003820038200382003820038
10024200371500000006119822251001010100001010000501423880120018200372003718588318767100102010000203000020037200371110021109101010000100100004036403162419907010000102003820038200382003820038
10024200371500000006119822251001010100001010000501423880020018200372003718588318767100102010000203000020037200371110021109101010000100100000006403164419907010000102003820038200382003820038
10024200371500000006119822251001010100001010000501423880020018200372003718588318767100102010000203000020037200371110021109101010000100100000006404164419907010000102003820038200382003820038
100242003715000000047119822251001010100001010000501423880020018200372003718588318767100102010000203000020037200371110021109101010000100100000006404164419981010000102003820038200382003820038
10024200371500000006119822251001010100001010000501423880020018200372003718588318767100102010000203000020037200371110021109101010000100100000006404164319907010000102003820038200382003820038
10024200371500000006119822251001010100001010000501423880120018200372003718588318767100102010000203000020037200371110021109101010000100100000006403164419907010000102003820038200382003820038

Test 2: uops

Code:

  fcsel h0, h1, h0, lt
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611822251000100010001368802018203720371716318951000100030002037203711100110001000073116111907100020382038203820382038
10042037150611822251000100010001368802018203720371716318951000100030002037203711100110001000073116111907100020382038203820382038
10042037150611822251000100010001368802018203720371716318951000100030002037203711100110001000073116111907100020382038203820382038
10042037150611822251000100010001368802018203720371716318951000100030002037203711100110001000073116111907100020382038203820382038
10042037150611822251000100010001368802018203720371716318951000100030002037203711100110001000073116111907100020382038203820382038
10042037150611822251000100010001368802018203720371716318951000100030002037203711100110001000090116111907100020382038203820382038
10042037150611822251000100010001368802018203720371716318951000100030002037203711100110001000073116111907100020382038203820382038
10042037150611822251000100010001368802018203720371716318951000100030002037203711100110001000073116111907100020382038203820382038
10042037150611822251000100010001368802018203720371716318951000100030002037203711100110001000073116111907100020382038203820382038
10042037150611822251000100010001368802018203720371716318951000100030002037203711100110001000073116111907100020382038203820382038

Test 3: Latency 1->3

Code:

  fcsel h0, h1, h0, lt
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000006119822251010010010000100100005001423880120018200372003718566318745101002001000020030000200372003711102011009910010010000101000071011611199070100001002003820038200382003820038
10204200371500000103198222510100100100001001000050014238801200182003720037185663187451010020010000200300002003720037111020110099100100100001010023710116111990726100001002003820038200382003820038
102042013215100206119822251010010010000100100005001423880020018200372003718566318745101002001000020030000200372003711102011009910010010000101001371011611199070100001002003820038200382003820038
102042003715000006119822251010010010000100100005001423880120018200372003718566318745101002001000020030000200372003711102011009910010010000101001371011621199070100001002003820038200382003820085
10204200371500001210319822251010010010000100100005001423880120018200372003718566318745101002001000020030000200372003711102011009910010010000101001071011611199070100001002003820038200382003820038
102042003715000008419767251010010010000100100005001423880120018200372003718566318745101002001000020030000200372003711102011009910010010000101001371011611199070100001002003820038200382003820038
102042003715000006119822251010010010000100100005001423880120018200372003718566318745101002001000020030000200372003711102011009910010010000101000071011611199070100001002003820038200382003820038
102042003715000006119822251010010010000100100005001423880020018200372003718566318745101002001000020030000200372003711102011009910010010000101000071011611199070100001002003820038200382003820038
102042003715000006119822251010010010000100100005001423880120018200372003718566318745101002001000020030000200372003711102011009910010010000101000071031611199070100001002003820038200382003820038
102042003715000006119822251010010010000100100005001423880120018200372003718566318745101002001000020030000200372003711102011009910010010000101000071011611199070100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000726198222510010101000010100005014238800200182003720037185883187671001020100002030000200372003711100211091010100001001000640316221990710000102003820038200382003820038
10024200371500084198222510010101000010100005014238800200182003720037185883187671001020100002030000200372003711100211091010100001001000640216221990710000102003820038200382003820038
10024200371500061198222510010101000010100005014238800200182003720037185883187671001020100002030000200372003711100211091010100001001000640216221990710000102003820038200382003820038
10024200371500061198222510010101000010100005014238800200182003720037185883187671001020100002030000200372003711100211091010100001001000640216221990710000102003820038200382003820038
10024200371500061198222510010101000010100005014238800200182003720037185883187671001020100002030000200372003711100211091010100001001000640216221990710000102003820038200382003820038
10024200371500061198222510010101000010100005014238800200182003720037185883187671001020100002030000200372003711100211091010100001001000640216221990710000102003820038200382003820038
10024200371500061198222510010101000010100005014238800200182003720037185883187671001020100002030000200372003711100211091010100001001000640216221990710000102003820038200382003820038
10024200371500061198222510010101000010100005014238800200182003720037185883187671001020100002030000200372003711100211091010100001001000640216221990710000102003820038200382003820038
10024200371500061198222510010101000010100005014238800200182003720037185883187671001020100002030000200372003711100211091010100001001000640216221990710000102003820038200382003820038
10024200371500061198222510010101000010100005014238800200182003720037185883187671001020100002030000200372003711100211091010100001001000640249221990710000102003820038200382003820038

Test 4: Latency 1->4

Chain cycles: 2

Code:

  fcsel h0, h1, h2, lt
  fcmp d0, d3
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
2020440037299000006139822252020020020000200200001100285388014001840037400373731633749520200200200002005000040037400371120201100991002000010000000013101161139909100100001004003840038400384003840038
2020440037299000006139822252020020020000200200001100285388014001840037400373731633749520200200200002005000040037400371120201100991002000010000000013101161139909100100001004003840038400384003840038
2020440037300000006139822252020020020000200200001100285388014001840037400373731633749520200200200002005000040037400371120201100991002000010000000013101161139909100100001004003840038400384003840038
20204400372990000158239822252020020020000200200001100285388014001840037400373731633749520200200200002005000040037400371120201100991002000010000000013101161139909100100001004003840038400384003840038
2020440037300000006139822252020020020000200200001100285436814001840037400373731633749520200200200002005000040037400371120201100991002000010000000013101161139909100100001004003840038400384003840038
20204400373000000072639822252020020020000200200001100285388014001840037400373731633749520200200200002005000040037400371120201100991002000010000000013101161139909100100001004003840038400384003840038
2020440037299000066139822252020020020000200200001100285388014001840037400373731633749520200200200002005000040037400371120201100991002000010000000013101161139909100100001004003840038400384003840038
2020440037300000006139822252020020020000200200001100285388014001840037400373731633749520200200200002005000040037400371120201100991002000010000000013101161139909100100001004003840038400384003840038
2020440037300000006139822252020020020000200200001100285388014001840037400373731633749520200200200002005000040037400371120201100991002000010000000013101161139909100100001004003840038400384003840038
2020440037300000006139822252020020020000200200001100285388014001840037400373731633749520200200200002005000040037400371120201100991002000010000000013101161139909100100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
2002440037300110000067398222520020202000020200001102853880040018400374003737338337517200202020000205000040037400371120021109102000010000000127010161011399091010000104003840038400384003840038
2002440037299000000061398222520020202000020200001102853880040018400374003737338337517200202020000205000040037400371120021109102000010000000127010161010399091010000104003840038400384003840038
2002440037310000030061398222520020202001220200001102853880040018400374003737338337517200202020000205000040037400371120021109102000010000000127010161111399091010000104003840038400384003840038
200244003730000000006139822252002020200002020000110285388004001840037400373733833751720020202000020500004003740037112002110910200001000000012709161011399091010000104003840038400384003840038
2002440037300000000061398222520020202000020200001102853880040018400374003737338337517200202020000205000040037400371120021109102000010000000127010161011399091010000104003840038400384003840038
2002440037300000000072639822252002020200002020000110285388004001840037400373733833751720020202000020500004003740037112002110910200001000000012701116910399091010000104003840038400384003840038
200244003729900000006139822252002020200002020000110285388004001840037400373733833751720020202000020500004003740037112002110910200001000000012709161011399091010000104003840038400384003840038
20024400373000000000613982225200202020000202000011028538800400184003740037373383375172002020200002050000400374003711200211091020000100000001270111698399091010000104003840038400384003840038
20024400373000000000613982225200202020000202000011028538800400184003740037373383375172002020200002050000400374003711200211091020000100000001270816910399091010000104003840038400384003840038
20024400372990000000613982225200202020000202000011028538800400184003740037373383375172002020200002050000400374003711200211091020000100000001271916810399091010000104003840038400384003840038

Test 5: throughput

Count: 8

Code:

  fcsel h0, h8, h9, lt
  fcsel h1, h8, h9, lt
  fcsel h2, h8, h9, lt
  fcsel h3, h8, h9, lt
  fcsel h4, h8, h9, lt
  fcsel h5, h8, h9, lt
  fcsel h6, h8, h9, lt
  fcsel h7, h8, h9, lt
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)l2 tlb miss data (0b)1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802044003830000002642580100100800001008000050064000014001940038400382997032999680100200800002002400004003840038118020110099100100800008010000511382479400350800001004003940039400394003940039
80204400382991000264258010010080000100800005006400001400194003840038299703299968010020080000200240000400384003811802011009910010080000801000051131116910400350800001004003940039400394003940039
80204400383001000264258010010080000100800005006400001400194003840038299703299968010020080000200240000400384003811802011009910010080000801000051139161111400350800001004003940039400394003940039
802044003830010002642580100100800001008000050064000014001940038400382997032999680100200800002002400004003840038118020110099100100800008010000511391699400350800001004003940039400394003940039
802044003830010002642580100100800001008000050064000014001940038400382997033002880100200800002002400004003840038118020110099100100800008010000511391699400350800001004003940039400394003940039
8020440038299100026425801001008000010080000500640000140019400384003829970329996801002008000020024000040073400381180201100991001008000080100005113101699400350800001004003940039400394003940039
8020440038300100026425801001008000010080000500640000140019400384003829970329996801002008000020024000040038400381180201100991001008000080100005113916911400350800001004003940039400394003940039
802044003829910002642580100100800001008000050064000014001940038400382997032999680100200800002002400004003840038118020110099100100800008010000511391699400350800001004003940039400394003940039
8020440038299100022542580100110800001008000050064000014001940038400382997032999680100200800002002400004003840038118020110099100100800008010000511391699400350800001004003940039400394003940039
802044003830010002642580100100800001008000050064000014001940038400382997032999680100200800002002400004003840038118020110099100100800008010000511391699400350800001004003940039400394003940039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024400383000000043258001010800001080000506400001400194003840038299923300188001020800002024000040038400381180021109101080000800100010993050200716354003580000104003940039400394003940039
800244003830000000432580010138000010800005064000004001940234400382999233001880010208000020240000400384003811800211091010800008001000009050200616534003580000104003940039400394003940039
800244023230000000432580010108004710800005064000014001940038400382999233001880010208000020240000400384003811800211091010800008001000006250200516534003580000104003940039400394003940039
8002440038300000004325800101080000108000050640000140019400384003829992330018800102080000202400004003840038118002110910108000080010000012050200616574003580000104003940039400394003940039
8002440038299000026443258001010800001080000506400001400194003840038299923300188001020800002024000040038400381180021109101080000800100000204050200516454003580000104003940039400394003940039
80024400383000003003012580010108000010800005064000014005740038400382999233001880010208022920240000400384003811800211091010800008001003006050200316534003580000104003940039400394003940039
8002440038300000004325800101080000108000050640000140019400384003829992330018800102080000202400004003840038118002110910108000080010000012050200516564003580000104003940039400394003940039
800244003829900000432580010108000010800005064000014001940038400382999233001880010208000020240000400384003811800211091010800008001000006050200316534003580000104003940039400394003940039
80024400382990100043258001010800001080000506400001400194003840038299923300188001020800002024000040184400381180021109101080000800100000138050200316464003580000104003940039400394003940039
800244003830000000432580010108000010800005564000014001940038400383005833001880010208000020240000400384003811800211091010800008001000009050200516644003580000104003940039400394003940039