Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTAS (scalar, D to D)

Test 1: uops

Code:

  fcvtas d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037231210325472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003020303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816003018303730372414328951057100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110001073116112629100030383038303830383038
10043037231210325472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110001073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000373116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816003018303730372414328951000100010003037303711100110001073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtas d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e1f3f4e5051schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372330000612954702510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071021611296330100001003003830038300383003830038
10204300372330000612954702510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000003071011611296330100001003003830071300383003830038
10204300372330000612954702510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000003071011611296330100001003003830038300383003830038
102043003723200007262954702510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611297050100001003003830038300383003830038
102043003723300008452954702510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
10204300372330000612954702510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
10204300372330000612954702510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000010071011611296330100001003003830038300383003830038
10204300372330000612954702510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003723300120612954702510100100100001001000050042776340300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830069
10204300372410000612954702510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acc2cfl1i tlb miss demand (d4)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003724100000115295472510010101000010100005042771600300183300373003728286252876710010201017820100003003730037111002110910101000010000006400316432962910000103003830038300383003830038
10024300372410000053929547251001010100001010000504277160130018030037300372828632878810010201000020100003003730037111002110910101000010020006400416442962910000103003830038300383003830038
100243003723300024046729547251001010100001010000504277160030018030037300372828632876710010201000020100003003730037111002110910101000010000006400416342964010000103003830038300383003830038
1002430037241000006129547251001010100001010000504277160030018030037300372828632876710010201000020100003003730037111002110910101000010000006400416432962910000103003830038300383008530038
10024300372460000023229547251001010100001010000504277160030018030037300372828632876710010201000020100003003730037111002110910101000010010006400416432962910000103013130132301333013330132
1002430131242101132240199529529611003912100081110158714284777030018030037300372828632876710010201000020100003003730037111002110910101000010000006400416432962910000103003830038300383003830038
10024300372410000025329547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000006400316342962910000103003830038300383003830038
100243003724100015018029547251001010100001010000504277160130018030037300372828632876710158201000020100003003730037111002110910101000010020006400416342962910000103003830038300383003830083
1002430037241000006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000006400416342962910000103003830038300383003830038
10024300372410000072629547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000306400416342962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtas d0, d8
  fcvtas d1, d8
  fcvtas d2, d8
  fcvtas d3, d8
  fcvtas d4, d8
  fcvtas d5, d8
  fcvtas d6, d8
  fcvtas d7, d8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)1e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815500003025801081008000810080020500640132020020020039200399977699908012020080032200800322003920039118020110099100100800001002011151181160020036800001002004020040200402004020040
802042003915500003025801081008000810080020500640132020020020039200399977699908012020080032200800322003920039118020110099100100800001002311151180160020036800001002004020040200402004020040
8020420039156000021425801081008000810080020500640132020020020039200399977699908012020080032200800322003920039118020110099100100800001004011151180160020036800001002004020040200402004020040
802042003915600003025801081008000810080020500640132020020020039200399977699908012020080032200800322003920039118020110099100100800001001011151180160020036800001002004020040200402004020040
802042003915600003025801081008000810080020500640132020020020039200399977699908012020080032200800322003920039118020110099100100800001000611151180160020036800001002004020040200402004020040
80204200391560000695258010810080008100800205006401320200200200392003999776999080120200800322008003220039200392180201100991001008000010040011151180160020036800001002004020040200402004020040
802042003915500009525801081008000810080020500640132020020020039200399977699908012020080032200800322003920039118020110099100100800001002011151180160020036800001002004020040200402004020040
80204200391560000302580108100800081008002050064013202002002003920039997769990801202008003220080032200392003911802011009910010080000100447811151180160020036800001002004020040200402004020040
8020420039155000074925801081008000810080020500640132020020020039200399977699908012020080032200800322003920039118020110099100100800001005011151180160020036800001002004020040200402004020040
802042003915500003025801081008000810080020500640132020020020039200399977699908012020080032200800322003920039118020110099100100800001009311151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)daddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420051155200000000040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502011601120036080000102004020040200402004020040
8002420039155000000000040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502011601120036080000102004020040200402004020040
8002420039155000000000040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502011601120036080000102004020040200402004020040
8002420039155000000000040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502011601120036080000102004020040200402004020040
8002420039156000000000040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502011601120036080000102004020040200402004020040
8002420039155000000000040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502011601120036080000102004020040200402004020040
8002420039155000000000040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502011601120036080000102004020040200402004020040
8002420039155000000000040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000010000502011601120036080000102004020040200402004020040
8002420039155000000000040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502011601120036080000102004020040200402004020040
8002420039155000000000040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502011601120036080000102004020040200402004020040