Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTAS (scalar, D to W)

Test 1: uops

Code:

  fcvtas w0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000037311611538100010001000542542542542542
2004541408525300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000407311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtas w0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8a9accdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300389740000013002311941725401001010020000100001002000010000500621497914801034113001301300381300381255343126246301002001000020000200100002000013003813003811202011009910010100100001000100000000131012162212959910007100001000010100130039130067130039130039130039
3020413003897400063013002311941725401001010020000100001002000010000500621497914801034013001301300381300381255103126246301002001000020000200100002000013003813003811202011009910010100100001000100000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000013002311946025401001010020000100001002000010000500621497914801034113001301300381300381255293126246302722001000020000200100002000013003813003811202011009910010100100001000100000060131012162212952510000100001000010100130039130039130039130039130039
302041300389740000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381255233126246301002001000020000200100002000013003813003811202011009910010100100001000100000001131012162212952510000100001000010100130039130039130039130039130039
302041300389740000013002311941725401001010020000100001002000010000500621497914801034113001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000000131013162212959510000100001000010100130039130039130039130039130041
302041300389740000013002311941736401001010020000100011002000010000500621502714801034113001301300381300381255703126246301002001000020000200100002000013003813003811202011009910010100100001000100000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000013002611941725401001010020000100001002000010000500621497914801034113001301300391300381255263126246301002001000020000200100002000013003813003811202011009910010100100001000100000000131012162212957010000100001000010100130039130039130040130039130039
302041300389750000013002311941725401001010020000100001002000010000500621497914801034113001301300381300381255383126246301002001000020000200100002000013003813003911202011009910010100100001000100001000131012162212952510000100001000010100130039130039130039130039130039
302041300389730000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381255253126246301002001000020000200100002000013003813003811202011009910010100100001000100000000131011162212952510000100001000010100130039130039130039130039130039
302041300389740000013002311942225401001010020000100001002000010000500621497914801034013001301300381300411254833126246301002001000020000200100002000013003813003811202011009910010100100001000100000000131012162212952510001100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0307090b18191e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8a9acbranch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038974000000130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013003813003811200211090101001010000100100000000012703162212952510000100001000010010130039130039130039130039130039
300241300389740000024130023119466254001010010200001000010200001000050621497914800025113001513003813004012549831262683001020100002012120100002000013004013007311200211090101001010000100100000060012702162212952810000100001000010010130039130039130039130039130140
30024130042974100000130023119417254001010010200001000010201201000050621497914800025013001313003913003812549831262683001020100002000020100002000013003813003811200211090101001010000100100000000012702162212952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002000013003813003811200211090101001010000100100000000012702162212952510000100001000010010130041130040130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002000013003813003811200211090101001010000100100000000012703162212952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013004113011311200211090101001010000100100000000012702162212952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013003813003811200211090101001010000100100000000012703162312952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002000013003813003811200211090101001010000100100004030012702162212952510004100001000010010130039130039130039130039130039
30024130038974000100130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002000013003813006211200221090101001010000100100000000012702162212952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621694714800025013001313003813003812549831262713001020100002000020100002000013003813012011200211090101001010000100100000000012702162212952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtas w0, d8
  fcvtas w1, d8
  fcvtas w2, d8
  fcvtas w3, d8
  fcvtas w4, d8
  fcvtas w5, d8
  fcvtas w6, d8
  fcvtas w7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0308090a0b18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a6a8acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400533100000000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000001115117016004003880000080000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000001115117016004003880000080000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000001115117016004003880000080000801004004240042400424004240042
160204400413110000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000001115117016004003880000080000801004012140121400424004240042
160204400413100000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000001115117016004003880000080000801004004240042400424004240042
160204400413100000000032252401048010016000410216002050014401320400704004140041199776199921601202001600322001600324004140041118020110099100801001000000001115117016004003880000080000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000001115117016004003880000080000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000001115117016004003880000080000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401320400224004140041199776199921601202021600322001600324004140041118020110099100801001000000001115117016004003880000080000801004012440042400424004240042
16020440041310000000006972524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000021001115117016004003880000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03081e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8a9acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160024400552990007072524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100000503011611400388000080000800104004240042400424004240042
16002440041299000422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010101000503011611400388000080000800104004240042400424004240042
160024400413110004225240281801041600001016000050144000004002240041401191999623200211600102016021420160000400414012311800211091080010101402503032511400388000080000800104004240042400424004240042
1600244004131302191322322524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100000503011611400388000080000800104004240042400424004240042
16002440041300000422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100030503011611400388000080000800104004240042400424004240042
16002440041300000422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100000503111611400388000080000800104004240042400424004240364
160024400413000330422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100000503011611400388000080000800104004240042400424004240042
16002440041300000422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100000503111611400388000080000800104004240042400424004240130
160024400413000001372524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100000503011611400388000080000800104004240042400424004240042
16002440041300000422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100000503011611400388000080000800104012840042400424004240042