Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTAS (scalar, D to X)

Test 1: uops

Code:

  fcvtas x0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)030a0b18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a1a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541400000043253000100020002000180000522541541248327420002000200054154111100110000007321622538100010001000542542542542542
20045414000015043253000100020002000180000522541541248327420002000200054154111100110000007321622538100010001000542542542542542
2004541400003043253000100020002000180000522541541248327420002000200054154111100110000007321622538100010001000542542542542542
2004541400000043253000100020002000180000522541541248327420002000200054154111100110000107321622538100010001000542542542542542
2004541400000043253000100020002000180000522541541248327420002000200054154111100110000007321622538100010001000542542637542542
20045414000093043253000100020002000180001522541541248327420002000200054154111100110000007321622538100010001000542542542542542
2004541400000043253000100020002000180000522541541248327420002000200054154111100110000007321622538100010001000542542542542542
2004541400000064253000100020002000180000522541541248327420002000200054154111100110000007321622538100010001000542542542542542
2004541400000043253000100020002000180000522541541248327420002000200054154111100110000107321622538100010001000542542542542542
2004541400000043253000100020002000180000522541541248327420002000200054154111100110000007321622538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtas x0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8a9acc2c5c9branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30204130038975000000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000013002311941725401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000000131012163212952510000100001000010100130039130039130039130039130040
3020413003897400008940013002311941725401001010020000100001002000010000500621502714801034013001313003813003812547631262493010020010000200002001000020000130038130038112020110099100101001000010001000000000000131012162212952510000100001000010100130051130081130039130040130039
30204130038974000000013002311941725401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000000131012162212958510000100001000010100130039130039130039130042130039
30204130038974000000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000000131012162212952510000100001000010100130039130039130039130039130039
302041300899740000000130023119417254010010100200001000010020000100005006214979148010340130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000002100000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000013002311945325401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000927352013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000180013002311941725401001010020000100001002000010050500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000000131013412212967210030100001000010100130128130039130039130122130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03070a0b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8acc5cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3002413003897400000001300231194172540010100102000010000102000010000506214979148000251130013013003813003812552131262683001020100002000020100002000013003813003811200211091010010100001010000000127041651312952510000100001000010010130039130039130039130039130039
30024130038974000000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312628430010201000020000201000020000130138130038112002110910100101000010100000001270141651312952510000100001000010010130039130039130039130039130104
3002413009997400000001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001010000000127051651312952510000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701316101312952510000100001000010010130039130039130039130039130039
30024130038974000000013002511945225400101001020000100001020000100005062149791480002501300130130038130038125498312626930010201000020000201000020000130038130038112002110910100101000010100000001270141613712952510000100001000010010130039130039130039130039130039
30024130038973000000013002511941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000001270131613612952510000100001000010010130039130039130039130039130039
300241300389740000000130023119417464001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701316131212952510000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000110200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701316121312952510000100001000010010130039130039130039130039130039
30024130038974000000013002311941725400101001020000100001020000100005062149791480002501300130130041130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000001270111651312952510000100001000010010130068130043130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000201312010000200001300381300381120021109101001010000101000000012701316111312952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtas x0, d8
  fcvtas x1, d8
  fcvtas x2, d8
  fcvtas x3, d8
  fcvtas x4, d8
  fcvtas x5, d8
  fcvtas x6, d8
  fcvtas x7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0307080a0b18191e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa1a6a8a9acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16020440062311000000000742524010480100160004100160020500144013204002204004140041199776199921601202001600322001600324004140041118020110099100801001000054000111511701600400388000080000801004004240042400424004240042
1602044004131000000000053252401048010016000410016002050014401321400220400414004119977619992160120200160032200160032400414004111802011009910080100100006000111511701600400388000080000801004004240042400424004240042
1602044004131100000000032252401048010016000410016002050014401321400220400414004119977619992160120200160032200160032400414004111802011009910080100100007000111511701600400388000080000801004004240042400424004240042
160204400413100000000005072524010480100160004100160020500144013204002204004140041199776199921601202001600322001600324004140041118020110099100801001000048000111511701600400388000080000801004004240042400424004240042
16020440041310000000000322524010480100160004100160020500144013204002204004140041199776199921601202001600322001600324004140041118020110099100801001000036000111511701600400388000080000801004004240042400424004240042
1602044004131100000000032252401048010016017610016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100008000111511701600400388000080000801004004240042400424004240042
1602044004131000000000032252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100008000111511701600400388000080000801004004240042400424004240042
1602044004131100000000010772524010480100160004100160020500144013204002204004140041199776199921601202001600322001600324004140041118020110099100801001000010120111511701600400388000080000801004004240042400424004240042
1602044004131000000000032252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100002000111511701600400388000080000801004004240042400424004240042
16020440041310000000000203252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100004000111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a8accficache miss (d3)d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16002440042300042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010005605020041632400388000080000800104004240042400424004240042
16002440041300042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010004405020021633400388000080000800104004240042400424004240042
1600244004129904225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101000695020031634400388008080000800104004240042400424004240042
16002440041300042252400108001016000010160000501440000040022400414004119996320021160214201600002016000040041400411180021109108001010003905020031644400388000080000800104004240042400424004240042
16002440041300042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010002505020031633400388000080000800104004240042400424004240042
16002440041300042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010004305020031633400388000080000800104004240042400424004240042
16002440041300042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010006125020041623400388000080000800104004240042400424004240042
16002440041299784225240010800101600001016000050144000004002240041400412002332002116001020160000201600004004140041118002110910800101000035020031632400388000080000800104004240042400424012840042
16002440041299042252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010006805020041633400388000080000800104004240042400424004240042
16002440041300042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010341395020031623400388000080000800104004240042400424004240042