Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTAS (scalar, H to W)

Test 1: uops

Code:

  fcvtas w0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtas w0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8acc2c5cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3020413003897400000001300231194552540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001001000000010131012163212952510000100001000010100130039130039130039130112130039
3020413003897400000001300231194502540100101002000010000100200001000054362149791480103411300131300381300401254763126249301002001000020000200100002000013003813003811202011009910010100100001001000000000131012163312952510000100001000010100130039130039130098130486130039
30204130217974110048019201300231194482540100101002000010000100200001000050062150271480103411300131300381300381254763126246301002001000020000200100002000013003813004011202011009910010100100001001000010000131012162212952510000100001000010100130039130039130039130087130040
3020413003897400000001300231194212540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013023213003811202011009910010100100001001000000000131012162312952510000100001000010100130039130039130039130121130039
3020413003897400000001300231194192540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001001000000000131013162212952510000100001000010100130039130039130039130084130039
3020413003897400000001300231194192540100101002000010002100200001000050062181491480137711300131300381300381254763126300301002001000020000200100002000013003813003811202011009910010100100001001000020000131012162312952510000100001000010100130039130039130039130125130039
3020413003897400000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001001000000000131012163312952510000100001000010100130039130039130039130070130039
3020413003897400000001300231194212540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001001000000000131013163212952510000100001000010100130039130039130039130098130039
3020413003897400000001300231194562540100101002000010000100200001000050062176501480103411300151300381301101254763126246301002001000020000200100002000013003813003811202011009910010100100001001000000000131013163212952510000100001000010100130039130039130039130108130039
3020413003897400000001300231194292540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001001000000000131013163312952510000100001000010100130039130039130039130039130046

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030a0b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8acc2cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3002413003897400013630013002311941725400101001020000100001020000100005062149791480002501300131301341300451254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130039130039
30024130038973000000013002311941725400101001020000100001020000100005062149791480002501300131300931300471254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130039130040
30024130038975000090013002311941725400101001020000100001020000100005062149791480002501300131300531300921254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130039130039
30024130038974000000013002311941725400101001020000100001020000100005062149791480002501300131300381301211254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012702161112952510000100001000010010130039130039130039130039130039
30024130038974000000013002311941725400101001020000100001020000100005062149791480002511300131300381300881254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130039130039
30024130038974000400013002311941725400101001020000100001020000100005062149791480002501300131300961300411254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130039130039
30024130038974000000013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012703161112952510000100001000010010130039130039130039130039130039
30024130038974000000013002311941725400101001020000100001020000100005062149791480002511300131300391300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000060012701161112952510000100001000010010130039130039130039130039130039
300241300389740000120013002311941725400101001020000100001020000100005062149791480002501300131300431300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952710000100001000010010130078130051130039130042130039
30024130038974000000013002311941725400101001020000100001020115100005062150271480002511300131300391300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtas w0, h8
  fcvtas w1, h8
  fcvtas w2, h8
  fcvtas w3, h8
  fcvtas w4, h8
  fcvtas w5, h8
  fcvtas w6, h8
  fcvtas w7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030818191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a8acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400613000001207412124010480100160004100160020500144013214030240041400412000106200341601202001600322001604384012040202318020110099100801001002210111511713410400388000080000801004004240042400424004240042
160204400413000113482323249240408802981603881021604525001443918040022400414004120000015200341605462001600322001600324042540195218020110099100801001000000111511701600400388000080000801004004240042400424004240042
1602044004130000000742524010480100160004100160020500144013204002240041400411997706199921601202001600322001600324004140041118020110099100801001000003111511701600400388000080000801004004240042400424004240042
1602044004130000000322524010480100160004100160020500144013204002240041400411997706199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
16020440041310000210966662224763082608162348100160020786149070304195842635425162068502392129216602420416452620416663442349424283318020110099100801001000001240111511701600400388000080000801004004240042400424004240123
1602044004131000030532524010480100160188100160020500144013204002240041400411997706199921601202001600322001600324004140041118020110099100801001000006111511701600400388000080000801004004240042401404004240042
1602044004130000000322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
16020440041300000006972524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
1602044004130000000322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
1602044019130000000322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0304080a0b1e3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)6061696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8acc5cfd0icache miss (d3)itlb miss (d4)d5d6d9dadbddinst fetch restart (de)e0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244004230000003304225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100005021001151600014174003880000080000800104004240042400424004240042
16002440041300100000422524001080010160000101600005014400000040022400414004119996320021160010201600002016000040041400411180021109108001010000502050017160001784003880000080000800104004240042400424004240042
160024400413110000019125240010800101600001016000050144000005400224004140041199963200211600102016000020160000400414004111800211091080010100005020000171600011174003880000080000800104004240042400424004240042
160024400412990000004225240010800101600001016000050144000010400224004140041199963200211600102016000020160000400414004111800211091080010100005020000171600015174003880000080000800104004240042400424004240042
160024400413000000004225240010800101600001016000050144000015400224004140041199963200211600102016000020160000400414004111800211091080010100005020000171600017174003880000080000800104004240042400424004240042
1600244004130000000042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004012940041118002110910800101002405020500171600017174003880000080000800104004240042400424012840042
160024400413000000004225240010800101600001016000050144000010400224004140041199963200211600102016000020160000400414004111800211091080010100005020000171600017174003880000080000800104004240042400424004240042
160024400412990000004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100005020000171600017174003880000080000800104004240042400424004240042
1600244004129900000023225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100005020000171600017174003880000080000800104004240042400424004240042
160024400413000000004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100005020000181600016174003880000080000800104004240042400424004240042