Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTAS (scalar, H to X)

Test 1: uops

Code:

  fcvtas x0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200019906152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541504325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541434325300010002000200018000152254154124832742000200020005415411110011000107311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtas x0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)6061696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9e9fa0a1a6a7a8a9acc2c5branch mispredict (cb)cdcfd0d2d5d6ddinst fetch restart (de)e0? int output thing (e9)eald/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300389740000001300231194172540100101002000010000100200001000050062149791480103400130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000010000100000000000013101031622129525100000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103400130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000010000100000000000013101021622129525100000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103400130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000010000100000000000013101021623129525100000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103400130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000010000100000000000013101021622129525100000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103400130013130038130038125477312624630100200100002000020010000200001300381300381120201100991001010010000010000100000000000013101021622129525100000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103400130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000010000100000000001013101021622129525100000100001000010100130039130039130039130039130039
30204130038974000000130023119418254010010100200001000010020000100005006214979148010340013001313004613036212547631263903010020210000200002081024720486130039130360512020110099100101001000001000010000040228000013106021622129606100000100001000010100130039130039130039130039130039
302041300389740000001300231194152540100101002000010000100200001000050062149791480103400130013130038130038125476312624630268200100002000020010000200001300381300381120201100991001010010000010000100000003000013100021622129525100000100001000010100130044130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103400130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000010000100000000000013101021622129525100000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062152191480103400130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000010000100000000000013101021622129525100000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0304080b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8a9acc2c5branch mispredict (cb)cfd0d2icache miss (d3)d5d6d9dadbddinst fetch restart (de)e0? int output thing (e9)eaebecld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3002413004310170000000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126285300102010000200002010000200001300381300381120021109101001010000100010000000000012700001116000101412952510000000100001000010010130039130039130039130039130039
30024130038974000000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312628330010201000020000201000020000130038130038112002110910100101000010001000000000001270000131600012512952510000000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000012700001316000131312952510000000100001000010010130039130039130039130039130039
300251300389740000075013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626930010201000020000201000020000130038130038112002110910100101000010001000001000001270000131600013512952510002000100001000010010130039130039130042130039130048
30024130038974000000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312627130010201000020000201000020000130038130038112002110910100101000010001000000000001270000516000131212952510000000100001000010010130039130039130039130039130039
300241300389740000000130054119417254001010010200001000110200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000104410019100000012700001316000131412952510000000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010063200002010000200001300411300381120021109101001010000100010000000000012700001316000131312952510000000100001000010010130040130039130039130039130039
30024130038974000000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626930010201000020000201000020000130038130038112002110910100101000010001000000000001270000121600061212952510000000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621502714800025013001301300381300381254983126272300102010000200002010000200001300381300391120021109101001010000100010000000300012700001116000121312952510000000100001000010010130039130039130039130039130039
30024130038974000006013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312627130010201000020000201000020000130038130038112002110910100101000010001000000000001270000111600013612952510000000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtas x0, h8
  fcvtas x1, h8
  fcvtas x2, h8
  fcvtas x3, h8
  fcvtas x4, h8
  fcvtas x5, h8
  fcvtas x6, h8
  fcvtas x7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030708090b18191e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a6a7a8a9acc5branch mispredict (cb)cdcfd2d5d6inst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400623100000000003225240104801001600041001600205001440132040022400414004119977061999216012020001600322001600324004140041118020110099100801001000000000111511700160400388000080000801004004240042400424004240042
1602044004131000000000069725240104801001600041001600205001440132140022400414004119977061999216012020001600322001600324004140041118020110099100801001000000000111511700160400388000080000801004004240042400424004240042
16020440041310000000000322524010480100160004100160020500144013214002240041400411997706199921601202000160032200160032400414004111802011009910080100100000210628111511700160400388000080000801004004240042400424004240042
1602044004131000000000031525240104801001600041001600205001440132040022400414004119977061999216012020001600322001600324004140041118020110099100801001000000000111511700160400388000080000801004004240042400424004240042
160204400413100000000003225240104801001600041001600205001440132140022400414004119977061999216012020001600322001600324004140041118020110099100801001000000000111511700160400388000080000801004004240042400424004240042
160204400413100000000003225240104801001600041001600205001440132140022400414004119977061999216012020001600322001600324004140041118020110099100801001000000000111511700161400388000080000801004004240042400424004240042
160204400413100000000003225240104801001600041001600205001440132140022400414004119977061999216012020001600322001600324004140041118020110099100801001000000000111511700160400388000080000801004004240042400424004240042
160204400413100000000003225240104801001600041001600205001440132140022400414004119977061999216012020001600322001600324004140041118020110099100801001000000100111511700160400388000080000801004004240042400424004240042
160204400413100000000003225240104801001600041001600205001440132140022400414004119977061999216012020001600322001600324004140041118020110099100801001000000000111511700160400388000080000801004004240042400424004240042
160204400413100000000003225240104801001600041001600205001440132140022400414004119977061999216012020001600322001600324004140041118020110099100801001000000000111511701160400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0307091e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696b6d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a8accfd2d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160024400553000004225240010800101600001016000050144000001400220400414004119996032002116001020160000201600004004140041118002110910800101002105020141642400388000080000800104004240042400424004240042
16002440041300000422524001080010160000101600005014400000140022040041400411999603200211600102016000020160000400414004111800211091080010100305020041642400388000080000800104004240042400424004240042
16002440041300000422524001080010160000101600005014400000040022040041400411999603200211600102016000020160000400414004111800211091080010100405020041642400388000080000800104004240042400424004240042
16002440041300000422524001080010160000101600005014400000040022040041400411999603200211600102016000020160000400414004111800211091080010100005020021624400388000080000800104004240042400424004240042
160024400413000007072524001080010160000101600005014400000040022040041400411999603200211600102016000020160000400414004111800211091080010100005020041642400388000080000800104004240042400424004240042
16002440041300000422524001080010160000101600005014400000040022040041400411999603200211600102016000020160000400414004111800211091080010100105020021624400388000080000800104004240042400424004240042
16002440041311000422524001080010160000101600005014400000040022040041400411999603200211600102016000020160000400414004111800211091080010100135020021624400388000080000800104004240120400424004240042
16002440041310000422524001080010160000101600005014400000140022040041400411999603200211600102016000020160000400414004111800211091080010100005020041624400388000080000800104004240042400424004240042
160024400413000104225240010800101600001016000050144000001400220400414004119996037200211600102016000020160000400414004111800211091080010100305020041624400388000080000800104004240042400424004240042
16002440041300000422524001080010160000101600005014400000140022040041400411999653200211600102016000020160000400414004111800211091080010100205020041624400388000080000800104004240042400424004240042