Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTAS (scalar, S to W)

Test 1: uops

Code:

  fcvtas w0, s0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000152254154124832742000200020005415411110011000037311611538100010001000542542542542542
20045414124325300010002000200018000152254154124832742000200020005415411110011000037311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000037311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000137311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000137311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtas w0, s0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0318191e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8a9acc2c5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30204130038974000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125483612624130100200100022000620010002200061300381300381120201100991001010010000100001000000000111131701161112953310000100001000010100130039130039130039130039130039
302041300389740021130023119417254010010100200001000010020000100005006214979148012621130013130038130040125483612624230100200100022000620010002200061300381300381120201100991001010010000100221000000030111131701161112953410000100001000010100130039130039130039130039130039
302041300389740012130023119420254010010105200001000010020000100005006214979148010341130013130114130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000003060000131012163212952510000100001000010100130039130039130039130039130039
30204130040974000130023119417254010010100200001000010020000100005006214979148080101130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000130023119417254010010100200031000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300382120201100991001010010000100001000000000010131012162212952710000100001000010100130039130039130039130039130039
30204130038974000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0307080a0b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acc2c5cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)eald/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038974000000000130023119417254001010010200031000010200001000050621497914800025013001301300381300381254983126268306782010000200002010000200001300381300381120021109101001010000100010000000000127011613129525100000100001000010010130039130039130039130039130039
30024130038974000000000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010066200001300381300381120021109101001010000100010002700000127011621129525100000100001000010010130039130041130052130039130039
3002413003897400000000013002311941725400101001020000100001020000100005062149791480002501300130130038130040125504312626830010201000020000201000020000130039130038112002110910100101000010221005800145725400191514325811132434100000100001000010010131689131749131733131778131616
3002413169398831103616051584113331912109510514034110070201641009517261591242088633288415079737013220701323751324901263561481275343594726117162337926118992411513224813251935120021109101001010000102210032000000127011611129525100000100001000010010130039130039130039130039130039
30024130038974000000000130023119417254001010010200001000010200001000060621496814800048113001301300381300381255003126268300102010000200002010000200001300381300381120021109101001010000100010000000000127011645129527100020100001000010010130039130039130042130039130039
30024130038974000000000130023119417254001010015200001000010200001000055622045414800048013001301305571301391254983126478303462010183200002010000200001303791300381120021109101001010000100010010000000127211611129525100000100001000010010130039130039130039130039130039
30024130038974000000600130023119417254001010010200001000010200001000050621496814800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000127011611129525100000100001000010010130039130039130039130039130039
300241300389740000000001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831263523001020100002000020100002000013003813003811200211091010010100001000100000036000127221611129525100022100001000010010130039130039130039130039130039
30024130043974100000000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126321300122010000200002010000200001300381300381120021109101001010000100010000000001127011611129525100000100001000010010130039130039130039130039130039
30024130048974000000000130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126336300122010000200002010000200001300381300381120021109101001010000100010000000000127211611129525100000100001000010010130039130075130064130039130039

Test 3: throughput

Count: 8

Code:

  fcvtas w0, s8
  fcvtas w1, s8
  fcvtas w2, s8
  fcvtas w3, s8
  fcvtas w4, s8
  fcvtas w5, s8
  fcvtas w6, s8
  fcvtas w7, s8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire (01)cycle (02)03080b18191e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a6a8acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1602044006531000000003225240104801001600041001600205001440132140022400414004119977061999216012020016003220016003240041400411180201100991008010010000000111511701600400388000080000801004004240042400424004240042
1602044004131100000003225240104801001600041001600205001440132140022400414004119977061999216012020016003220016003240041400411180201100991008010010000000111511701600400388000080000801004004240042400424004240042
1602044004131000000003225240104801001600041001600205001440132140022400414004119977061999216012020016003220016003240041400411180201100991008010010000000111511701600400388000080000801004004240042400424004240042
1602044004131100000003225240104801001600041001600205001440132140022400414004119977061999216012020016003220016003240041400411180201100991008010010000000111511701600400388000080000801004004240042400424004240042
1602044004131100000003225240104801001600041001600205001440132140022400414004119977561999216012020016003220016003240041400411180201100991008010010000000111511701600400388000080000801004004240042400424004240042
1602044004131000000003225240104801001600041001600205001440132140022400414004119977061999216012020016003220016003240041400411180201100991008010010000000111511711600400388000080000801004004240042400424004240042
160204400413110000000322524010480100160004100160020500144013214002240041400411997701319992160120200160032200160032400414004111802011009910080100100003101115378116000406818158080000801004068341315413184124141396
1602044134632000171621211408123483932447768124616317610016348069814693681411644113341387203560139207051636022041633402041621164131441474181802011009910080100100000088281115330015100405668134080000801004114341154411594108741147
1602044124632010148184870403443184243876814641629801101614606321463648140861410624115320192011520309162546206162692202162876410014084214180201100991008010010000208370111523107900400388000080000801004004240042400424004240042
1602044004131000000003225240104801001600041001600205001440132140022400414004119977061999216012020016003220016003240041400411180201100991008010010000000111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030818191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a6a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005430000000422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000502041667400388000080000800104004240042400424004240042
1600244004130000000782524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000502061686400388000080000800104004240042400424004240042
1600244004130000000422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000502061634400388000080000800104004240042400424004240042
1600244004130000000422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000502041676400388000080000800104004240042400424004240042
1600244004130000000422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000502061643400388000080000800104004240042400424004240042
1600244004130000000422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000502041643400388000080000800104004240042401274004240042
16002440041304000007072524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000502031647400388000080000800104004240042400424004240042
1600244004130000000422524001080010160000101600005014400001400224004140041199963200211602302016000020160000400414004111800211091080010100000502081635400388000080000800104004240042400424004240042
1600244004130000000422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000502041666400388000080000800104004240042400424004240042
1600244004130000000422524001080010160000101600005014417681400224004140041199963200211600102016000020160000400414004111800211091080010100000502061676400388000080000800104004240042400424004240042