Firestorm: FCVTAS (scalar, S to W) measurements

Code:

  fcvtas w0, s0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	3	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	12	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	3	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	3	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	1	3	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	1	3	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtas w0, s0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	974	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125483	6	126241	30100	200	10002	20006	200	10002	20006	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1	1	1	1317	0	1	16	1	1	129533	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	21	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801262	1	130013	130038	130040	125483	6	126242	30100	200	10002	20006	200	10002	20006	130038	130038	1	1	20201	100	99	100	10100	10000	100	2	2	10000	0	0	0	3	0	1	1	1	1317	0	1	16	1	1	129534	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	12	130023	119420	25	40100	10105	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130114	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	3	0	6	0	0	0	0	1310	1	2	16	3	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130040	974	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14808010	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	130023	119417	25	40100	10100	20003	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	2	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1	0	1310	1	2	16	2	2	129527	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130038	974	0	0	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20003	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30678	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	1270	1	16	1	3	129525	10000	0	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10066	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10002	7	0	0	0	0	0	1270	1	16	2	1	129525	10000	0	10000	10000	10010	130039	130041	130052	130039	130039
30024	130038	974	0	0	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130040	125504	3	126268	30010	20	10000	20000	20	10000	20000	130039	130038	1	1	20021	10	9	10	10010	10000	10	2	2	10058	0	0	145725	4	0	0	1915	14	325	8	11	132434	10000	0	10000	10000	10010	131689	131749	131733	131778	131616
30024	131693	988	3	1	1	0	3	6	1605	1584	1	133319	121095	1051	40341	10070	20164	10095	17	26159	12420	88	6332884	15079737	0	132207	0	132375	132490	126356	148	127534	35947	26	11716	23379	26	11899	24115	132248	132519	35	1	20021	10	9	10	10010	10000	10	2	2	10032	0	0	0	0	0	0	1270	1	16	1	1	129525	10000	0	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	60	6214968	14800048	1	130013	0	130038	130038	125500	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	1270	1	16	4	5	129527	10002	0	10000	10000	10010	130039	130039	130042	130039	130039
30024	130038	974	0	0	0	0	0	0	0	0	0	130023	119417	25	40010	10015	20000	10000	10	20000	10000	55	6220454	14800048	0	130013	0	130557	130139	125498	3	126478	30346	20	10183	20000	20	10000	20000	130379	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10010	0	0	0	0	0	0	1272	1	16	1	1	129525	10000	0	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	6	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214968	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	1270	1	16	1	1	129525	10000	0	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126352	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	36	0	0	0	1272	2	16	1	1	129525	10002	2	10000	10000	10010	130039	130039	130039	130039	130039
30024	130043	974	1	0	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126321	30012	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1	1270	1	16	1	1	129525	10000	0	10000	10000	10010	130039	130039	130039	130039	130039
30024	130048	974	0	0	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130038	130038	125498	3	126336	30012	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	1272	1	16	1	1	129525	10000	0	10000	10000	10010	130039	130075	130064	130039	130039

Test 3: throughput

Count: 8

Code:

  fcvtas w0, s8
  fcvtas w1, s8
  fcvtas w2, s8
  fcvtas w3, s8
  fcvtas w4, s8
  fcvtas w5, s8
  fcvtas w6, s8
  fcvtas w7, s8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40065	310	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	5	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	1	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	0	13	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	3	1	0	1	1	1	5378	1	160	0	0	40681	81580	80000	80100	40683	41315	41318	41241	41396
160204	41346	320	0	0	17	16	2121	1408	1	2348	393	244776	81246	163176	100	163480	698	1469368	1	41164	41133	41387	20356	0	139	20705	163602	204	163340	204	162116	41314	41474	18	1	80201	100	99	100	80100	100	0	0	0	0	8828	1	1	1	5330	0	151	0	0	40566	81340	80000	80100	41143	41154	41159	41087	41147
160204	41246	320	1	0	14	8	1848	704	0	3443	184	243876	81464	162980	110	161460	632	1463648	1	40861	41062	41153	20192	0	115	20309	162546	206	162692	202	162876	41001	40842	14	1	80201	100	99	100	80100	100	0	0	2	0	8370	1	1	1	5231	0	79	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40054	300	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	4	16	6	7	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	78	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	6	16	8	6	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	6	16	3	4	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	4	16	7	6	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	6	16	4	3	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	4	16	4	3	40038	80000	80000	80010	40042	40042	40127	40042	40042
160024	40041	304	0	0	0	0	0	707	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	3	16	4	7	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160230	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	8	16	3	5	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	4	16	6	6	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1441768	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	6	16	7	6	40038	80000	80000	80010	40042	40042	40042	40042	40042

FCVTAS (scalar, S to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations