Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTAS (scalar, S to X)

Test 1: uops

Code:

  fcvtas x0, s0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
200454150004325300010002000200018000052254154124832742000200020005415411110011000000073011611538100010001000542542542542542
200454140004325300010002000200018000052254154124832742000200020005415411110011000000073011611538100010001000542542542542542
200454140004325300010002000200018000052254154124832742000200020005415411110011000000073011611538100010001000542542542542542
200454140004325300010002000200018000052254154124832742000200020005415411110011000000073011611538100010001000542542542542542
200454150004325300010002000200018000052254154124832742000200020005415411110011000000073011611538100010001000542542542542542
200454140004325300010002000200018000052254154124832742000200020005415411110011000000073011611538100010001000542542542542542
200454140004325300010002000200018000052254154124832742000200020005415411110011000000073011611538100010001000542542542542542
200454140004325300010002000200018000052254154124832742000200020005415411110011000000073011611538100010001000542542542542542
200454150004325300010002000200018000052254154124832742000200020005415411110011000001073011611538100010001000542542542542542
200454140004325300010002000200018000052254154124832742000200020005415411110011000010073011611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtas x0, s0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
302041300389740000090130054119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000100131012162212952510000100001000010100130039130039130039130039130039
302041300389740000000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300621300381120201100991001010010000100010000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381301101120201100991001010010000100010000000131012162212952510000100001000010100130039130039130039130039130039
302041300469740000000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020410000200001300381300381120201100991001010010000100010000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000000130023119417254010010100200001000010020000100005116215075148010341130013130038130038125476312624630100200100002000020010000200001300421300381120201100991001010010000100410007000131012163212952510000100001000010100130039130039130039130039130039
302041300389740000000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000660131012162212952710000100001000010100130041130039130039130039130039
302041300389740000000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000000130243119455254012410100200031000010020000100005006215027148073441130016130040130038125478312624630266200100002012220010061200001300381300391120201100991001010010000100010000500131012162212952510000100001000010100130039130039130039130039130040
302041300389830000160130023119417254010010100200001000010020000100005006214979148010341130013130041130116125476312624630100200100002072920010000201221300401300381120201100991001010010000100010000000132912162212952510000100001000010100130039130039130039130039130124
302041300389740000000130025119417254010010100200031000010020000100005006214979148010341130013130132130040125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0e2? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
3002413003810700002400130023119417384001010010200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002013213005113003811200211091010010100001000100000000127021611129525010000100001000010010130040130039130039130040130039
300241300381008000000130023119415254001010010200001000012200001000050621544514802850113001313003813003812549831262683018120100002000020100002000013003813003811200211091010010100001000100000000127011611129525010000100001000010010130039130039130039130039130039
300241300381008000000130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000060127011611129525010000100001000010010130039130039130039130039130039
300241300381007000000130023119417254001010010200001000010200001000050621507514800025013001613003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000127011621129525010000100001000010010130039130039130039130039130039
300241300381008000000130029119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001002100000043380130511611129525010000100001000010010130039130039130040130039130039
300241300381008000000130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013004113003811200211091010010100001000100001000127011621129525010000100001000010010130039130039130039130039130039
300241300381008000000130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262713001020100002000020100002000013003813003811200211091010010100001000100000000127011611129525010000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621544514800025013001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000127011611129525010000100001000010010130039130039130039130039130039
30024130038974000000130023119418254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000127011611129525010000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000127011611129525010000100001000010010130039130063130039130075130054

Test 3: throughput

Count: 8

Code:

  fcvtas x0, s8
  fcvtas x1, s8
  fcvtas x2, s8
  fcvtas x3, s8
  fcvtas x4, s8
  fcvtas x5, s8
  fcvtas x6, s8
  fcvtas x7, s8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400413100010000002222524010480100160004100160020500144013204008340041400411997761999216012020016003220016003240041400411180201100991008010001000000150111511901600400388000080000801004004240042400424004240042
160204400413110000000003225240104801001600041001608505001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100010000001170111511701600400388000080000801004004240042400424004240042
16020440041311000000000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010001000000990111511701610400388000080000801004004240042400424004240042
160204400413101000000007425240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100010000001260111511701600400388000080000801004004240042400424004240042
1602044004131000100000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801000100000007111511701600400388000080000801004004240042400424004240042
16020440041311000000120032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801000100000060111511701600400388000080000801004004240042400424004240042
1602044004131000000000078252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801000100000000111511701600400388000080000801004004240042400424004240042
16020440041310000000600322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010001002072000111511701600400388000080000801004004240042400424004240042
16020440041311000000000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010001000071000111511701600400388000080000801004004240042400424004240042
160204400413100000000004122524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010001000072000111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)daddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400423000422524001080010160000101600005014436081040022400414004119996320021160010201600002016000040041400411180021109108001010202147502000216032400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400000040022400414004119996320021160010201600002016000040041400411180021109108001010000153502001216044400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100000502051416033400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400000040022400414004119996320021160010201600002016000040041400411180021109108001010000171502051216033400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400000040022400414004119996320021160010201600002016000040041400411180021109108001010000144502000216022400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000015400224004140041199963200211600102016000020160000400414004111800211091080010100009502051316032400388000080000800104004240042400424004240042
160024400413000323252400108001016000010160000501440000104002240041400411999632002116001020160000201600004004140041118002110910800101000099502051316032400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100003502051216022400388000080000800104004240042400424004240042
16002440041300042252400108001016000010160000501440000154002240041400411999632002116001020160000201600004004140041118002110910800101000018502051216023400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400001040022400414004119996320021160010201600002016000040041400411180021109108001010000141502051416042400388000080000800104004240042400424004240042