Firestorm: FCVTAS (vector, 4H) measurements

Code:

  fcvtas v0.4h, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	inst ldst (9b)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	0	61	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	0	61	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	3	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	0	89	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	24	1	0	0	103	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	12	61	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	1	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	0	61	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	3	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	0	61	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2547	44	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	1	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->2

Code:

  fcvtas v0.4h, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	224	0	405	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	726	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	631	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	9	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	6	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29633	1	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	298	29547	25	10100	104	10000	100	10000	500	4277160	0	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	0	61	29547	25	10017	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	0	0	0	0	1436	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10012	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	0	61	29547	25	10012	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	669	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	8	5	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	0	61	29547	25	10010	12	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28773	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038

Test 3: throughput

Count: 8

Code:

  fcvtas v0.4h, v8.4h
  fcvtas v1.4h, v8.4h
  fcvtas v2.4h, v8.4h
  fcvtas v3.4h, v8.4h
  fcvtas v4.4h, v8.4h
  fcvtas v5.4h, v8.4h
  fcvtas v6.4h, v8.4h
  fcvtas v7.4h, v8.4h

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20058	155	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	2	16	2	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	155	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	1	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	2	16	2	2	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	155	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	2	16	2	2	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	155	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	2	16	2	2	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	155	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	2	16	1	2	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	155	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5239	2	119	2	2	20329	1	80000	100	20401	20406	20406	20406	20448
80204	20398	158	0	0	5	5	825	528	2263	160	80776	100	80779	101	80822	500	645606	0	20309	20406	20417	10048	37	10101	80832	200	80843	202	80721	20418	20407	8	1	80201	100	99	100	100	80000	100	0	0	0	0	0	3098	2	1	1	1	5233	6	115	3	5	20045	0	80000	100	20049	20049	20049	20049	20049
80204	20048	156	0	0	0	0	0	0	1632	83	80395	100	80370	102	80309	500	642500	0	20029	20048	20201	10008	35	10145	80334	202	80346	202	80558	20315	20048	4	1	80201	100	99	100	100	80000	100	4	4	0	0	0	3	0	2	2	2	5128	3	23	3	3	20127	0	80000	100	20049	20050	20049	20205	20206
80204	20049	156	0	0	0	0	0	0	64	26	80116	100	80016	100	80028	500	640196	0	20029	20048	20048	9976	10	9986	80128	200	80038	200	80038	20049	20049	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	2	2	2	5128	3	23	2	3	20046	0	80000	100	20049	20050	20050	20049	20049
80204	20048	155	0	0	0	0	0	0	64	26	80116	100	80016	100	80028	500	640196	0	20029	20048	20048	9976	9	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	2	2	2	5128	3	23	3	2	20045	0	80000	100	20049	20049	20049	20050	20049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20050	155	0	0	82	25	80010	10	80000	10	80000	50	640000	0	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20036	80000	10	20040	20040	20040	20040	20092
80024	20039	156	1	0	40	25	80010	10	80000	10	80000	50	640000	0	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	10011	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	40	25	80010	10	80000	10	80000	50	640000	0	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	40	25	80010	10	80000	10	80000	50	640000	0	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	1	0	0	5020	1	16	1	1	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	62	25	80010	10	80000	10	80000	50	640000	0	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	40	25	80010	10	80000	10	80000	50	640000	0	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	156	0	0	40	25	80010	10	80000	10	80000	50	640000	0	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	40	25	80010	10	80000	10	80000	50	640000	0	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20036	80000	10	20040	20040	20040	20040	20040

FCVTAS (vector, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations