Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTAU (scalar, D to W)

Test 1: uops

Code:

  fcvtau w0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000052254154124832742000200020005415411110011000007341611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414154325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtau w0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9d9fa6a8abacdtlb miss (c1)c2branch mispredict (cb)cfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30204130043120100000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100000100100003700000131012161212952510000100001000010100130039130039130039130039130039
302041300411008000240013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100000100100000210000131012162212952710000100001000010100130039130039130039130039130039
3020413003810080000011300231194172540106101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000010010000000000131012162212958010000100001000010100130039130039130039130039130039
30204130038100800000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100000100100002008101133512162212952510000100001000010100130039130039130039130039130039
3020413003810080000001300231194662540100101002000010001100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000010010000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003810080009001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300821300451120201100991001010010000010010000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003810080000001300231194712540100101002000010000100200001000050062149791480103401300130130038130038125479312624630100200100002000020010000200001300381300381120201100991001010010000010010000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003810080000001300231194192540130101002000010000100200001000050062149791480103411300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000010010000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003810080000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125498312624730100200100002000020010000200001300381300411120201100991001010010000010010000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003810080000001300231194173540100101002000010000100200001000050062149791480103411300130130039130038125476312624630100200100002000020010000200001300381300381120201100991001010010000010010000000000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030918191e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a7a8a9acc2branch mispredict (cb)cdcfd2d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038100800001300231194172540010100102000010000102000010000506214979148000250130013130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000000000127003165412952510000100001000010010130039130039130039130039130039
30024130038100800001300231194172540010100102000010000102000010000506214979148000250130013130041130038125498312626830010201000020000201000020000130038130038112002110910100101000010100010000000127004164412952510000100001000010010130039130039130039130039130039
30024130038100800001300231194172540010100102000010000102000010000506214979148000250130013130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000000000127004166512952510000100001000010010130039130039130069130039130039
300241300389740000130023119417254001010010200001000010200001000050621497914800025013001313003813003812549819126324300102010000200002010000200001300381300381120021109101001010000101000000033000127005164412952510000100001000010010130039130039130039130039130039
3002413003897400001300231194172540010100102000010000102000010000506214979148000250130013130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000000000127004165412952510000100001000010010130039130039130075130081130039
3002413003897400001300231194172540010100132000010000102000010000506214979148000250130013130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000000000127005165512952510000100001000010010130039130039130039130039130039
3002413003897400001300231194172540010100102000010000102000010000506214979148000250130013130038130038125498312626830177201000020000201000020000130038130038112002110910100101000010100000100000127004165712960710000100001000010010130039130039130039130039130039
3002413003897400001300231194172540010100102000010000102000010000506215075148089260130013130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100120103000127004165512952510000100001000010010130039130039130039130039130039
30024130038974000961300231194182540010100102000010000102000010000506214979148000250130013130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000000000127004164512952510000100001000010010130039130039130039130039130039
30024130038974000013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300761120021109101001010000101000000000001270051642212955910000100001000010010130041130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtau w0, d8
  fcvtau w1, d8
  fcvtau w2, d8
  fcvtau w3, d8
  fcvtau w4, d8
  fcvtau w5, d8
  fcvtau w6, d8
  fcvtau w7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0318191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16020440053311001203225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
1602044004131000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
1602044004131000007425240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100030111511701600400388000080000801004004240042400424004240042
1602044004131000004625240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
1602044004131100003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
1602044004131100003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701610400388000080000801004004240042400424004240042
1602044004131000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
1602044004131000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400654006340053
1602044005131000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
1602044004131000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03080a0b18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa6a8a9accfd0d2icache miss (d3)d5d6d9ddinst fetch restart (de)e0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16002440055310000000022025240010800101600001016000050144000001400220400414004119996320021160010201600002016000040041400411180021109108001010000050200005160444003880000080000800104004240042400424004240042
16002440041310000000042225240010800101600001016000050144000001400220400414004119996320021160010201600002016000040041400411180021109108001010000050200005160554003880000080000800104005340042400424004240042
1600244004131000000004225240010800101600001016000050144000001400220400414004119996320021160010201600002016000040041400411180021109108001010000050200003160554003880000080000800104004240042400424004240042
1600244004131100000004225240010800101600001016000050144000001400220400414004119996320021160010201600002016000040041400411180021109108001010010050200002160334003880000080000800104004240042400424004240042
1600244004131000000004225240010800101600001016000050144000000400220400414004119996320021160010201600002016000040041400411180021109108001010000050200005160444003880000080000800104004240042400424004240042
16002440041310000000070725240010800101600001016000050144000001400220400414004119996320021160010201600002016000040041400411180021109108001010000050200005160554003880000080000800104004240042400424004240042
1600244004131000000004225240010800101600001016000050144000001400220400414004119996320021160010201600002016000040041400411180021109108001010000350200004160244003880000080000800104004240042400424004240042
1600244004131000000004225240010800101600001016000050144000001400220400414004119996320021160010201600002016000040041400411180021109108001010000350200005160444003880000080000800104004240042400424004240042
1600244004131100000004225240010800101600001016000050144000001400220400414004119996320021160010201600002016000040041400411180021109108001010020050200004160444003880000080000800104004240042400424004240042
1600244004131100000008425240010800101600001016000050144000001400220400414004119996320021160010201600002016000040041400411180021109108001010000050200004160344003880000080000800104004240042400424004240042