Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTAU (scalar, D to X)

Test 1: uops

Code:

  fcvtau x0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)03071e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a0a7a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
200454140043253000100020002000180005225415412483274200020002000541541111001100000007321633538100010001000542542542542542
200454140043253000100020002000180005225415412483274200020002000541541111001100000007321633538100010001000542542542542542
200454140043253000100020002000180005225415412483274200020002000541541111001100000007331633538100010001000542542542542542
200454140643253000100020002000180005225415412483274200020002000541541111001100000007331633538100010001000542542542542542
200454140043253000100020002000180005225415412483274200020002000541541111001100000007331633538100010001000542542542542542
200454140043253000100020002000180005225415412483274200020002000541541111001100000007331633538100010001000542542542542542
200454150043253000100020002000180005225415412483274200020002000541541111001100000007331633538100010001000542542542542542
200454140043253000100020002000180005225415412483274200020002000541541111001100000007331633538100010001000542542542542542
200454140043253000100020002000180005225415412483274200020002000541541111001100000007331633538100010001000542542542542542
200454140043253000100020002000180005225415412483274200020002000541541111001100000007321633538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtau x0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8a9acc2c5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)eald/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3020413003897400000013002311941725401001010020000100001002000010000500621497914801034113001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001001000000000001310111622129525100000100001000010100130039130039130039130039130039
3020413003897500000013002311941725401001010020000100001002000010000500621497914801034113001501300381300381254763126246301002001000020000200100622000013003813003811202011009910010100100001001000000000001310121622129525100000100001000010100130039130039130039130039130039
3020413003897400000013002311941725401001010020000100001002000010000500621497914801034113004401300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001001000010000001310121622129525100000100001000010100130039130039130039130039130039
3020413003897400000013002311941725401311010020000100001002000010000500621497914801034113001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001001000000000001310121622129525100000100001000010100130039130039130039130039130039
3020413003897400000013002311941725401001010020000100001002000010000582621517114801145113001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001001000000000001310121622129525100000100001000010100130039130039130039130039130039
3020413003897400000013002411941725401001010020000100001002000010000500621497914801034113001301300381300411254763126246301002001000020000200100002000013003813003811202011009910010100100001001000010000001310121622129525100000100001000010100130039130039130039130041130039
3020413003897400000013002311941725401001010020000100001002000010000500621497914801034113001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001001000000000001310121622129525100000100001000010100130039130071130039130039130039
3020413003897400000013002311941725401001010020000100001002000010000500621497914801034113001401300381300411254763126246301002001000020000200100002000013003813003811202011009910010100100001001000000000001310121622129586100000100001000010100130039130039130039130039130039
30204130038974000900130025119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000002167000001383147722129525100260100001000010100130039130039130039130039130039
30204130038973000000130023119417464010610100200001000410020232100005006214979148060441130013013003813003812547620126246301002001000020000200100002000013003813003811202011009910010100100001001000010000001348121622129528100000100001000010100130039130204130039130368130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03070b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8a9acc2branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3002413003897400000013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300391300381120021109101001010000101000000000012703162212952510000100001000010010130039130049130039130039130039
3002413003897400003013002311941725400101001020000100001020000100005062149791480002511300131300381300381255013126268300102010000200002010000200001300381300431120021109101001010000101000000000012703162212952510000100001000010010130039130039130039130039130039
30024130038974000015013002711941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000000012702162212952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000020012702162212952510000100001000010010130039130039130040130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000000012702162212952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062154451480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000000012702162212952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000000012702162212952510000100001000010010130040130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000000012702162212952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002501300131300741300941254983126268300102010000200002010000200001300381300381120021109101001010000101000000001012703162212952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000000012702162212952510000100001000010010130040130039130039130039130073

Test 3: throughput

Count: 8

Code:

  fcvtau x0, d8
  fcvtau x1, d8
  fcvtau x2, d8
  fcvtau x3, d8
  fcvtau x4, d8
  fcvtau x5, d8
  fcvtau x6, d8
  fcvtau x7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a8a9acc2c5branch mispredict (cb)cdcfd5d6e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16020440066310126322524010480100160004100160020500144013204002204004140041199776199921601202001600322001600324004140041118020110099100801001000002101115117016400388000080000801004004240042400424004240042
16020440041310010182524010480100160004100160020500144013204002204004140041199776199921601202001600322001600324004140041118020110099100801001000001801115117016400388019880000801004004240042400424004240042
160204400413100532524010480100160004100160020500144013204002204004140041199776199921601202001600322001600324004140041118020110099100801001002109660211153730151410788113280000801004091240992406714004240042
16020440041310332252401048010016000410016002050014401321400220400414004119977619992160120200160032200160032400414004111802011009910080100100000001115117016400388000080000801004004240042400424004240042
160204400413103707252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100010001115117016400388000080000801004004240042400424004240042
16020440041311632252401048010016000410016002050014401321400220400414004119977619992160120200160032200160032400414004111802011009910080100100000301115117016400388000080000801004004240042400424004240042
16020440041311619872532427028106016276810416230450014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100012301115117016400388000080000801004004240042400424004240042
16020440041311032252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100000001115117016400388037480000801004004240042400424004240042
16020440041310032252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100000001115117016400388000080000801004004240042400424004240042
16020440041310032252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100000001115117016400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0308091e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa6a8acc2cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16002440042300004208625240010800101600001016000050144000014002240041400411999632002116001020160000201600004004140041118002110910800101000000502015161010400388000080000800104004240042400424004240042
160024400413001100422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100100050201116137400388000080000800104004240042400424004240042
1600244004130000004247240284801991602041016020650144000014002240041400411999632002116001020160000201600004004140041118002110910800101000000507012161111400388000080000800104004240042400424004240042
1600244004130000004225240311800101600001016000050144000014036240041400411999632002116019420160000201602004012440041118002110910800101000020502015431211400388000080000800104004240042400424004240042
16002440041300001206325240010800101600001016000050144000014002240041400411999632002116001020160000201600004004140041118002110910800101000000502013161113400388000080000800104004240042400424004240042
16002440041300001206325240010800101600001016000050144000014002240041400411999632002116001020160000201600004004140041118002110910800101000000502012161112413298000080000800104004240042400424004240042
16002440041300000042252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010204423005020111699403248000080000800104004240042400424004240042
1600244004130000004225240010800101600001016000050144000014002240041400412009332002116001020160000201600004004140041118002110910800101000113080050201016911400388000080000800104004240042400424004240042
1600244173132400129681622524001080010160000101633325014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000050201116137400388000080000800104004240042400424004240042
1600244004131600004225240010800101600001016000050144000014002240041400411999632002116001020160000201600004004140234118002110910800101000000502011161212400388000080000800104004240042400424004240042