Firestorm: FCVTAU (scalar, D to X) measurements

Code:

  fcvtau x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	2	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	2	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	3	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	6	43	25	3000	1000	2000	2000	18000	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	3	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	3	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	3	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	5	0	0	43	25	3000	1000	2000	2000	18000	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	3	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	3	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	3	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	2	16	3	3	538	1000	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtau x0, d0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	0	1310	1	1	16	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	975	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130015	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10062	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130044	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	1	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40131	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	582	6215171	14801145	1	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130024	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	0	130038	130041	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	1	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130041	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	0	10000	10000	10100	130039	130071	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130014	0	130038	130041	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129586	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	9	0	0	130025	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	0	0	21670	0	0	0	0	1383	1	4	77	2	2	129525	10026	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	973	0	0	0	0	0	0	130023	119417	46	40106	10100	20000	10004	100	20232	10000	500	6214979	14806044	1	130013	0	130038	130038	125476	20	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	1	0	0	0	0	0	0	1348	1	2	16	2	2	129528	10000	0	10000	10000	10100	130039	130204	130039	130368	130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130039	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	1270	3	16	2	2	129525	10000	10000	10000	10010	130039	130049	130039	130039	130039
30024	130038	974	0	0	0	0	3	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	130038	130038	125501	3	126268	30010	20	10000	20000	20	10000	20000	130038	130043	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	1270	3	16	2	2	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	15	0	130027	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	1270	2	16	2	2	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	2	0	0	1270	2	16	2	2	129525	10000	10000	10000	10010	130039	130039	130040	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	1270	2	16	2	2	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6215445	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	1270	2	16	2	2	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	1270	2	16	2	2	129525	10000	10000	10000	10010	130040	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	1270	2	16	2	2	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130074	130094	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1	0	1270	3	16	2	2	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	1270	2	16	2	2	129525	10000	10000	10000	10010	130040	130039	130039	130039	130073

Test 3: throughput

Count: 8

Code:

  fcvtau x0, d8
  fcvtau x1, d8
  fcvtau x2, d8
  fcvtau x3, d8
  fcvtau x4, d8
  fcvtau x5, d8
  fcvtau x6, d8
  fcvtau x7, d8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40066	310	126	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	21	0	1	1	1	5117	0	16	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	1018	25	240104	80100	160004	100	160020	500	1440132	0	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	18	0	1	1	1	5117	0	16	40038	80198	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	53	25	240104	80100	160004	100	160020	500	1440132	0	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	2	1	0	9660	2	1	1	1	5373	0	151	41078	81132	80000	80100	40912	40992	40671	40042	40042
160204	40041	310	3	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	3	707	25	240104	80100	160004	100	160020	500	1440132	0	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	1	0	0	0	1	1	1	5117	0	16	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	6	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	3	0	1	1	1	5117	0	16	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	6	1987	253	242702	81060	162768	104	162304	500	1440132	0	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	1	2	3	0	1	1	1	5117	0	16	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	40038	80374	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	40038	80000	80000	80100	40042	40042	40042	40042	40042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40042	300	0	0	42	0	86	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	15	16	10	10	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	1	1	0	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	1	0	0	0	5020	11	16	13	7	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	42	47	240284	80199	160204	10	160206	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5070	12	16	11	11	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	42	25	240311	80010	160000	10	160000	50	1440000	1	40362	40041	40041	19996	3	20021	160194	20	160000	20	160200	40124	40041	1	1	80021	10	9	10	80010	10	0	0	0	2	0	5020	15	43	12	11	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	12	0	63	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	13	16	11	13	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	12	0	63	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	12	16	11	12	41329	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	2	0	4423	0	0	5020	11	16	9	9	40324	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	20093	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	11308	0	0	5020	10	16	9	11	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	41731	324	0	0	12	968	162	25	240010	80010	160000	10	163332	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	11	16	13	7	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	316	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40234	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	11	16	12	12	40038	80000	80000	80010	40042	40042	40042	40042	40042

FCVTAU (scalar, D to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations