Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTAU (scalar, H to W)

Test 1: uops

Code:

  fcvtau w0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
200454140043253000100020002000180000522541541248327420002000200054154111100110007311611538100010001000542542542542542
200454140043253000100020002000180000522541541248327420002000200054154111100110007311621538100010001000542542542542542
200454140043253000100020002000180000522541541248327420002000200054154111100110007311611538100010001000542542542542542
200454140043253000100020002000180000522541541248327420002000200054154111100110007321611538100010001000542542542542542
200454140043253000100020002000180001522541541248327420002000200054154111100110007321611538100010001000542542542542542
200454140043253000100020002000180000522541541248327420002000200054154111100110007321611538100010001000542542542542542
200454140043253000100020002000180000522541541248327420002000200054154111100110007311611538100010001000542542542542542
200454140043253000100020002000180001522541541248327420002000200054154111100110007311611538100010001000542542542542542
200454130043253000100020002000180000522541541248327420002000200054154111100110007311611538100010001000542542542542542
200454140043253000100020002000180000522541541248327420002000200054154111100110007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtau w0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
3020413003897400000001300231194172540100101002000010000100200001000050062149791480103413001313003813003812548361262413010020010002200062001000220006130038130038112020110099100101001000010001000000000111131701161112982210000100001000010100130041130039130039130039130039
3020413003897401000001300231194172540100101002000010000100200001000050062149791480103413001313037013004012548371262413010020010002200062001000220006130038130038112020110099100101001000010001000000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400100001300231194172540100101002000010000100200001000050062149791480103413001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000001300231194172540100101002000010000100200001000050062149791480103413004313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010041000000000000131012162212952810000100001000010100130039130041130039130039130039
302041300389740000573001300231194172540100101302000010000100200001000050062149791480103413001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000000131012482212956110000100001000010100130284130040130042130039130039
3020413003997410000001300231194532540100101002000310000100200001000050062203201480148013001313003913037712547631262463010020210245200002001000020000130038130038112020110099100101001000010001000000000000131012162212973410000100001000010100130040130165130039130039130039
3020413003897400000001300231194172540100101002000010000100200001000053262151711480103413001313003813003812547731262463010020210000200002001000020000130038130038112020110099100101001000010001000000000000131012162212952610000100001000010100130039130039130039130039130039
3020413003897400000001300231194172540100101002000010000100200001000050062149791480103413001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000001300231194172540100101002000010000100200001000050062149791480103413001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000000131012163212952510000100001000010100130039130039130039130039130039
30204130040974000000013002311941725401001010020000100001002000010000500621497914801376130013130038130038125476312624630100204100002000020010000200001300381300381120201100991001010010000100010000000120001131012482312954110000100001000010100130039130125130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
3002413006697500000901300231194172540010100102000010000102000010000506214979148000251130013130038130038125498312626830010201000020000201000020000130038130038112002110901010010100001000010000003240012702162212952510000100001000010010130039130039130039130039130039
300241301119740000000130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002012613003813003811200211090101001010000100001000020270012702163212952510000100001000010010130039130042130039130039130039
3002513006397400000001300231194172540010100102000010000102000010000506215267148000251130013130038130038125498312626830010201000020000201000020000130038130038112002110901010010100001000010000001320012703163212952510000100001000010010130039130039130039130039130039
300241300619770000001321300231194172540010100102000010000102000010000506214979148000250130013130038130038125498312626830010201000020000201000020000130038130038112002110901010010100001000010000003450012702162212952510000100001000010010130039130039130039130039130039
3002413007497400000001300231194172540010100102000010000102000010000506214979148000250130013130038130038125498312626830010201000020000201000020000130038130038112002110901010010100001000010000003960012702162212952510000100001000010010130039130039130039130039130039
3002413007897400000001300231194172540010100102000010000102000010000506214979148000250130013130038130038125498312626830010201000020000201000020000130038130038112002110901010010100001000010000003210012702162212958110000100001000010010130039130039130039130039130040
3002413006597400000001300231194522540010100102000010000102000010000506214979148000250130013130038130038125498312626830010201000020000201000020000130038130038112002110901010010100001000010000003660012702163212952510000100001000010010130039130039130039130039130039
3002413005697400000001300231194172540010100102000010000102000010000506214979148000250130013130038130038125498312626830010201000020000201000020000130038130038112002110901010010100001000010000001980013982802212952810004100001000010010132551132581132595132344132535
3002413191898900131273840272813269612054466840201100492009310059132255911274606249231148843590131566132127132246126360149127593346202411749229072511901230431325541326742812002110901010010100001002010050129009100175772262212952510000100001000010010130039130039130039130039132267
300241323109921012827356422881326861203476084017610044200811005415233631151960627513414942801113195313247313233512660918112779835135281177322664221000020000130038130038112002110901010010100001000010000002310012702163213153910000100001000010010130039130039130040130040130039

Test 3: throughput

Count: 8

Code:

  fcvtau w0, h8
  fcvtau w1, h8
  fcvtau w2, h8
  fcvtau w3, h8
  fcvtau w4, h8
  fcvtau w5, h8
  fcvtau w6, h8
  fcvtau w7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03091e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044006631100032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117016400388000080000801004004240042400424004240042
1602044004131003032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117016400388000080000801004004240042400424004240042
16020440041310012032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117016400388000080000801004004240042400424004240042
16020440041310000697252401048010016000410016002050014401321400224004140041199986199921601202001600322001600324004140041118020110099100801001000001115117016400388000080000801004004240042400424004240042
1602044004131000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117016400388000080000801004004240042400424004240042
1602044004131000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117016400388000080000801004004240042400424004240042
1602044004131000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117016400388000080000801004004240042400424004240042
16020440041321012032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117016400388000080000801004004240042400424004240042
1602044004131000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117016400388000080000801004004240042400424004240042
1602044004131000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117016400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)0309181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2cfd2l1i cache miss demand (d3)d5map dispatch bubble (d6)daddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400423100004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100005020001160114003880000080000800104004240042400424004240042
160024400413100004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100005020001160114003880000080000800104004240042400424004240042
160024400413100004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100005020001160214003880000080000800104004240042400424004240042
160024400413100004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100005020001160224003880000080000800104004240042400424004240042
1600244004131000042252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000050200011601140038800002080000800104004240042400424004240042
160024400413110004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100005020001160114029580000080000800104004240042400424004240042
160024400413100004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100005020001160114003880000080000800104004240042400424004240042
160024400413100006325240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100005020001160114003880000080000800104004240042400424004240042
16002440041311000199625240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100005020001160114003880000080000800104004240042400424004240042
160024400413100034225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100005020001160114003880000080000800104004240042400424004240042