Firestorm: FCVTAU (scalar, H to W) measurements

Code:

  fcvtau w0, h0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	1	16	2	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	2	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	2	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	2	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	3	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtau w0, h0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	130038	130038	125483	6	126241	30100	200	10002	20006	200	10002	20006	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1	1	1	1317	0	1	16	1	1	129822	10000	10000	10000	10100	130041	130039	130039	130039	130039
30204	130038	974	0	1	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	130370	130040	125483	7	126241	30100	200	10002	20006	200	10002	20006	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	1	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130043	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	4	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129528	10000	10000	10000	10100	130039	130041	130039	130039	130039
30204	130038	974	0	0	0	0	573	0	0	130023	119417	25	40100	10130	20000	10000	100	20000	10000	500	6214979	14801034	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	1310	1	2	48	2	2	129561	10000	10000	10000	10100	130284	130040	130042	130039	130039
30204	130039	974	1	0	0	0	0	0	0	130023	119453	25	40100	10100	20003	10000	100	20000	10000	500	6220320	14801480	130013	130039	130377	125476	3	126246	30100	202	10245	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129734	10000	10000	10000	10100	130040	130165	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	532	6215171	14801034	130013	130038	130038	125477	3	126246	30100	202	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129526	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	3	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130040	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801376	130013	130038	130038	125476	3	126246	30100	204	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	12	0	0	0	1	1310	1	2	48	2	3	129541	10000	10000	10000	10100	130039	130125	130039	130039	130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130066	975	0	0	0	0	0	9	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	0	10	10010	10000	10	0	0	0	10000	0	0	324	0	0	1270	2	16	2	2	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130111	974	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20126	130038	130038	1	1	20021	10	9	0	10	10010	10000	10	0	0	0	10000	2	0	27	0	0	1270	2	16	3	2	129525	10000	10000	10000	10010	130039	130042	130039	130039	130039
30025	130063	974	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6215267	14800025	1	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	0	10	10010	10000	10	0	0	0	10000	0	0	132	0	0	1270	3	16	3	2	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130061	977	0	0	0	0	0	0	132	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	0	10	10010	10000	10	0	0	0	10000	0	0	345	0	0	1270	2	16	2	2	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130074	974	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	0	10	10010	10000	10	0	0	0	10000	0	0	396	0	0	1270	2	16	2	2	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130078	974	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	0	10	10010	10000	10	0	0	0	10000	0	0	321	0	0	1270	2	16	2	2	129581	10000	10000	10000	10010	130039	130039	130039	130039	130040
30024	130065	974	0	0	0	0	0	0	0	130023	119452	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	0	10	10010	10000	10	0	0	0	10000	0	0	366	0	0	1270	2	16	3	2	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130056	974	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	0	10	10010	10000	10	0	0	0	10000	0	0	198	0	0	1398	2	80	2	2	129528	10004	10000	10000	10010	132551	132581	132595	132344	132535
30024	131918	989	0	0	1	31	27	3840	2728	132696	120544	668	40201	10049	20093	10059	13	22559	11274	60	6249231	14884359	0	131566	132127	132246	126360	149	127593	34620	24	11749	22907	25	11901	23043	132554	132674	28	1	20021	10	9	0	10	10010	10000	10	0	2	0	10050	1	2	90091	0	0	1757	7	226	2	2	129525	10000	10000	10000	10010	130039	130039	130039	130039	132267
30024	132310	992	1	0	1	28	27	3564	2288	132686	120347	608	40176	10044	20081	10054	15	23363	11519	60	6275134	14942801	1	131953	132473	132335	126609	181	127798	35135	28	11773	22664	22	10000	20000	130038	130038	1	1	20021	10	9	0	10	10010	10000	10	0	0	0	10000	0	0	231	0	0	1270	2	16	3	2	131539	10000	10000	10000	10010	130039	130039	130040	130040	130039

Test 3: throughput

Count: 8

Code:

  fcvtau w0, h8
  fcvtau w1, h8
  fcvtau w2, h8
  fcvtau w3, h8
  fcvtau w4, h8
  fcvtau w5, h8
  fcvtau w6, h8
  fcvtau w7, h8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40066	311	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	3	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	12	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	697	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19998	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	321	0	12	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	40038	80000	80000	80100	40042	40042	40042	40042	40042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	cf	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40042	310	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	1	16	0	1	1	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	1	16	0	1	1	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	1	16	0	2	1	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	1	16	0	2	2	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	1	16	0	1	1	40038	80000	20	80000	80010	40042	40042	40042	40042	40042
160024	40041	311	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	1	16	0	1	1	40295	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	1	16	0	1	1	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	63	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	1	16	0	1	1	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	311	0	0	0	1996	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	1	16	0	1	1	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	3	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	1	16	0	1	1	40038	80000	0	80000	80010	40042	40042	40042	40042	40042

FCVTAU (scalar, H to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations