Firestorm: FCVTAU (scalar, H to X) measurements

Code:

  fcvtau x0, h0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	1	0	1	0	0	15	0	1	49	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	0	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	0	74	4	16	4	4	538	1000	1000	1000	542	542	542	542	542
2004	541	4	1	0	1	0	0	0	0	1	49	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	0	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	0	74	4	16	4	4	538	1000	1000	1000	542	542	542	542	542
2004	541	4	1	0	1	0	0	0	0	1	49	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	0	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	0	74	4	16	4	4	538	1000	1000	1000	542	542	542	542	542
2004	541	4	1	0	1	0	0	0	0	1	49	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	0	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	0	74	4	16	4	4	538	1000	1000	1000	542	542	542	542	542
2004	541	4	1	0	1	0	0	0	0	1	49	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	0	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	0	74	4	16	4	4	538	1000	1000	1000	542	542	542	542	542
2004	541	4	1	0	1	0	0	0	0	1	49	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	0	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	0	74	4	16	4	4	538	1000	1000	1000	542	542	542	542	542
2004	541	4	1	0	1	0	0	0	0	1	49	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	0	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	0	74	4	16	4	4	538	1000	1000	1000	542	542	542	542	542
2004	541	4	1	0	1	0	0	0	0	1	49	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	0	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	0	74	4	16	4	4	538	1000	1000	1000	542	542	542	542	542
2004	541	4	1	0	1	0	0	9	0	1	49	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	0	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	0	74	4	16	4	4	538	1000	1000	1000	542	542	542	542	542
2004	541	4	1	0	1	0	0	0	0	1	49	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	0	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	0	74	4	16	4	4	538	1000	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtau x0, h0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	0	130038	130038	125483	7	126242	30100	200	10002	20006	200	10002	20006	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1	1	1	1317	0	1	16	1	1	129533	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	1	0	0	12	0	0	130042	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130375	130038	125483	7	126241	30100	200	10002	20006	200	10002	20492	130039	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1	1	1	1317	0	1	16	1	1	129534	10008	10000	10000	10100	130039	130039	130039	130039	130379
30204	130038	974	0	0	0	0	0	0	0	130028	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	0	130038	130038	125483	6	126242	30100	200	10002	20006	200	10002	20006	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	0	0	1	1	1	1318	0	1	16	1	1	129534	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119418	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	0	130038	130038	125483	7	126241	30100	200	10002	20006	200	10002	20006	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1	1	1	1317	0	2	16	1	1	129540	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130045	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130039	125484	7	126241	30100	200	10002	20006	200	10002	20006	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	2	0	0	1	1	1	1318	0	1	16	1	1	129536	10000	10000	10000	10100	130363	130039	130039	130039	130039
30204	130038	973	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125483	7	126242	30100	200	10002	20006	200	10002	20006	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1	1	1	1317	0	1	16	1	1	129536	10000	10000	10000	10100	130040	130039	130039	130039	130039
30204	130038	973	0	0	0	0	0	0	0	130049	119417	25	40141	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125483	6	126242	30100	200	10002	20006	200	10002	20006	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1	1	1	1317	0	1	16	2	1	129534	10006	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125483	7	126241	30265	200	10002	20006	200	10002	20006	130040	130368	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1	1	1	1318	0	1	16	1	1	129534	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130062	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125483	7	126242	30100	200	10002	20006	206	10002	20006	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1	1	1	1317	0	1	16	1	1	129533	10000	10000	10000	10100	130042	130039	130040	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130031	119417	25	40100	10100	20000	10000	100	20000	10000	628	6214979	14801034	1	130013	0	130038	130038	125630	7	126447	30100	200	10002	20006	200	10002	20006	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1	1	1	1317	0	1	16	1	1	129533	10000	10000	10000	10100	130045	130376	130039	130039	130042

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130038	974	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130038	130038	125498	3	126270	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	0	1	16	1	2	129525	10000	0	10000	10000	10010	130039	130039	130039	130039	130039
30024	130126	974	0	0	0	0	0	0	0	130023	119463	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130042	130038	125505	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	0	1	16	1	1	129525	10000	0	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	24	0	1	133026	120172	648	40177	10049	20082	10051	12	23140	11127	60	6278739	14938877	0	130013	0	130038	130043	125498	3	126268	30010	20	10000	20000	20	10000	20000	130044	130038	1	1	20021	10	9	10	10010	10000	10	10000	2	0	0	0	1270	0	1	16	1	1	129837	10001	0	10000	10000	10010	130532	130039	130365	132383	130375
30024	130473	974	2	2	2	2	1035	88	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130014	0	130038	130041	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	2	0	0	0	1270	0	1	16	2	1	129525	10000	0	10000	10000	10010	130039	130040	130039	130039	130039
30024	130038	1008	0	0	0	0	9	0	0	130024	119475	25	40010	10010	20000	10000	10	20000	10000	50	6217981	14800025	0	130013	0	130041	130039	125541	3	126268	30673	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	0	1	16	2	1	129525	10000	0	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	0	130023	119415	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30177	20	10000	20000	20	10000	20000	130038	130080	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	0	2	16	1	1	129525	10000	0	10000	10000	10010	130039	130039	130039	130039	130050
30024	130038	974	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	0	1	16	1	1	129525	10000	0	10000	10000	10010	130075	130074	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1	1270	0	1	16	1	1	129525	10000	0	10000	10000	10010	130039	130039	130039	130075	130042
30024	130038	974	0	0	0	0	0	0	0	130023	119417	40	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	0	1	16	1	1	129525	10000	0	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30677	20	10000	20000	20	10000	20000	130271	130120	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	0	1	16	1	1	129525	10000	0	10000	10000	10010	130039	130039	130039	130039	130039

Test 3: throughput

Count: 8

Code:

  fcvtau x0, h8
  fcvtau x1, h8
  fcvtau x2, h8
  fcvtau x3, h8
  fcvtau x4, h8
  fcvtau x5, h8
  fcvtau x6, h8
  fcvtau x7, h8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40075	300	0	0	0	0	0	317	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	1	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	299	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	396	0	160	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	2	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40055	299	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	52	0	3	0	0	5020	15	16	0	12	5	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	60	0	0	0	0	5020	14	16	0	13	7	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	9	0	0	5020	16	16	0	5	16	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	42	25	240010	80010	160000	10	160814	50	1440000	0	40022	40041	40041	19996	18	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	4	15	0	0	5020	7	16	0	5	16	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	232	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	120	0	0	5020	16	16	0	16	16	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	132	0	0	5020	6	16	0	7	13	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	1	0	129	0	0	5020	7	16	0	5	16	40038	80000	80000	80010	40042	40042	40120	40042	40120
160024	40041	316	0	1	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	1	0	132	0	0	5020	16	16	0	16	5	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	84	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	1	0	126	0	0	5020	13	16	0	5	16	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	153	0	0	5020	16	16	0	16	7	40038	80000	80000	80010	40042	40042	40042	40042	40042

FCVTAU (scalar, H to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations