Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTAU (scalar, S to W)

Test 1: uops

Code:

  fcvtau w0, s0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)030b3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8a9accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
20045414043253000100020002000180000522541541248327420002000200054154111100110000007311621538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110000007311621538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110000007311621538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110000007311621538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110000007311621538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110000037311622538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110000007311621538100010001000542542542542542
20045414064253000100020002000180001522541541248327420002000200054154111100110000007311622538100010001000542542542542542
20045414057253000100020002000180001522541541248327420002000200054154111100110000007311632538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110000007311621538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtau w0, s0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03070818191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8acbranch mispredict (cb)cfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300389740000001300921194172540100101002000310000100200001000053662149791480580301300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000030131012163212952510000100001000010100130364130044130039130039130043
3020413003897400000013006411941725401001010020000100001002000010000500621497914804076013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100003180131012162212952510000100001000010100130039130039130042130376130039
3020413003997400005101300671194172540100101002000010000100200001000050062149791480103411300131300381300381254783126246301002001000020000200100002000013003813003811202011009910010100100001000010000000131012162312956010000100001000010100130039130039130039130039130039
302041300389730000001304151194172540100101002000010000100200001000057862150271480103401300131300381300381254813126246301002001000020000200102452000013003813003811202011009910010100100001000010000030131012162212952910000100001000010100130039130039130039130039130039
3020413004297400000013007311941725401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000169980131012162212952510000100001000010100130039130039130039130039130039
302041300389740000001300381194172540117101002000010000100200001000050062150271480103401300131300421300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000131012162212952510002100001000010100130040130039130039130039130039
302041300389740000001300871194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400210013007911941825401001010020000100001002000010000500621497914801034113001313003813003812548931262473010020010183200002001000020000130038130038112020110099100101001000010000100000170630131013162212980110000100001000010100130039130039130039130039130039
302041300389740000001300451194172540100101002000010000100200001000050062149791480103411300131300381300381254763126256301002001000020000200100002000013003813003811202011009910010100100001000010000000131012162212952510000100001000010100130079130039130039130039130039
302041300389740000001300601194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000131012162312952510000100001000010100130039130039130039130039130045

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0318191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8a9acc2c5branch mispredict (cb)cfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038974000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000127002161112952510000100001000010010130039130042130039130039130039
3002413003897400001300231194173040010100102000010000102000010000506214979148000250130013013003813003812549831262723001020100002000020100002000013003813003811200211091010010100001001000000138000127001161112952510000100001000010010130039130039130039130039130039
30024130038974000013002311941725400101001020000100001020000100495062149791480002501300130130038130038125498312627230010201000020000201000020000130038130038112002210910100101000010010000000000127001161112952510000100001000010010130039130039130039130039130039
30024130038974000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312627530010201000020131201000020000130038130041112002110910100101000010010000009000127001161112952510000100001000010010130084130044130039130039130039
30024130038974000013002311941725400101001020000100001020000100005062149791480002511300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000127001331112952510000100001000010010130047130039130039130039130039
30024130038973000013002311941825400101001020000100001020000100005062149791480002511300130130041130038125501312631330010201000020000201000020130130038130075112002110910100101000010010000000200130601562112952510000100001000010010130039130039130039130039130039
30024130038974000013002311941725400101001020000100001020000100005062149791480002511300130130038130038125498312628730010201000020000201000020000130038130038112002110910100101000010010000103000127001161112952510000100001000010010130039130039130039130067130039
30024130042974009013002511941725400101001020000100001020000100005062149791480002511300130130041130038125498312631230010201000020000201000020000130038130038112002110910100101000010210000000000127001161112952510000100001000010010130039130039130039130039130039
30024130039974009013002311941725400101001020000100001020000100005062149791480002511300130130041130038125498312628130010201000020000201000020000130038130038112002110910100101000010010000000001127001161112952510000100001000010010130039130039130039130039130039
30024130038974000013002311941725400101001020000100001020000100005062149791480002511300130130038130038125498312627330010201000020000201000020000130038130038112002110910100101000010010000000000127001161112952510000100001000010010130039130039130039130039130065

Test 3: throughput

Count: 8

Code:

  fcvtau w0, s8
  fcvtau w1, s8
  fcvtau w2, s8
  fcvtau w3, s8
  fcvtau w4, s8
  fcvtau w5, s8
  fcvtau w6, s8
  fcvtau w7, s8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0308091e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400533000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100027111511711600400388000080000801004004240042400424004240042
160204400413000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100042111511701600400388000080000801004004240042400424004240042
160204400413000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100033111511701600400388000080000801004004240042400424004240042
160204400412990003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100027111511701600400388000080000801004004240042400424004240042
160204400413010003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100018111511701600400388000080000801004004240042400424004240042
160204400413000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100021111511701600400388000080000801004004240042400424004240042
1602044004130000054025240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100033111511701600400388000080000801004004240042400424004240042
160204400413190003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100033111511701600400388000080000801004004240042400424004240042
1602044004130000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000189111511701600400388000080000801004004240042400424004240042
16020440041300000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010036111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0307080a1e3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160024400553001010149252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502115161616400388000080000800104004240042400424004240042
160024400413001010149252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000502114161111400388000080000800104004240042400424004240042
160024400413001010149252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502115161615400388000080000800104004240042400424004240042
160024400413001010149252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502112161614400388000080000800104004240042400424004240042
1600244004130010101714252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000502116161515400388000080000800104004240042400424004240042
160024400413001010149252400108001016000010160000501440000014008540041400411999632002116001020160000201600004004140041118002110910800101000502116161111400388000080000800104004240042400424004240042
160024400412991010149252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502115161512400388000080000800104004240042400424004240042
16002440041300101014925240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100050218161514400388000080000800104004240042400424004240042
160024400413001010191252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101010502116161616400388000080000800104004240042400424004240042
160024400413001010149252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502117161416400388000080000800104004240042400424004240042