Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTAU (scalar, S to X)

Test 1: uops

Code:

  fcvtau x0, s0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541408525300010002000200018000052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541504325300010002000200018000052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541504325300010002000200018000052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541434325300010002000200018000052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541504325300010002000200018000154654154124832742000200020005415411110011000037321622538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtau x0, s0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030b191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8acc2c5cfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300389740000130023119417254010010100200041000010020000100005006214979148010340130013013009413005712547631262463010020010000200002001000020000130038130068112020110099100101001000010000100000000131012162212971110000100001000010100130039130039130039130039130039
302041300389740000130023119417254010010100200001000010020000100005006214979148010340130013013007413004112547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131013162212952510000100001000010100130039130039130039130039130039
302041300389740000130023119417254010010100200051000010020000100005006214979148010340130013013004113003812547631262463010020010000200002001000020000130077130055112020110099100101001000010000100000000131012162212952510000100001000010100130039130039130039130039130039
30204130076974003301300231194172540100101002000010000100200001000050062149791480103411300130130098130048125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000501859520131013253213002710017100001000010100130039130039130039130116130039
3020413003897400001300231194172540100101002000010000100200001000050062149791480103411300130130040130038125476312624630100200100002000020010000201291300511300381120201100991001010010000100001000005100131012162212952510000100001000010100130039130039130039130039130039
302041300389740000130023119417254010010100200001000010020000100005006214979148010340130013013006613003912547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012162212952510000100001000010100130039130072130039130039130039
302041300389740000130023119417254010010100200001000010020000100005006214979148010340130013013008013007112547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012162212966210000100001000010100130039130039130039130039130039
302041300389740000130024119417254010010100200001000010020000100005006214979148010340130013013006513004112547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000130023119417254010010100200001000010020000100005006214979148010340130013013005713004212547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000130023119417254010010100200001000010020000100005006214979148010340130013013008113003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03090b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8a9acc5branch mispredict (cb)cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ebld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
300241300381036000000130023119456254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000127051611129525100000100001000010010130039130039130039130086130039
300241300381008000000130023119429254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300681300381120021109101001010000100010000000000127011611129525100000100001000010010130039130039130039130090130039
300241300381007000000130023119417254001010010200001000010200001000050621497914800025113001301300381300381255073126268300102010000200002010000200001300381300381120021109101001010000100010000000000127011611129525100000100001000010010130039130049130258130443130039
3002413003997400000598130526119440254001010019200031000010200001000050621497914800025013001301300381301241254983126268300102010000200002010000200001300381300381120021109101001010000100010000000300127011611129527100000100001000010010130039130039130102130079130039
30024130038974000000130023119420254001010053200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000127011611129525100000100001000010010130039130039130039130087130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010005000000127011611129525100020100001000010010130043130039130090130053130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000129511611129525100000100001000010010130039130039130086130055130039
30024130038974000000130023119436254001010010200031000010200001000050621526714800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000127011611129525100000100001000010010130039130039130039130105130039
30024130038974000000130023119421254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000127011611129525100020100001000010010130039130042130039130066130039
300241300401072000000130061119418254001010010200001000010200001000050621497914800253013005901300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000127011611129525100000100001000010010130039130039130133130043130039

Test 3: throughput

Count: 8

Code:

  fcvtau x0, s8
  fcvtau x1, s8
  fcvtau x2, s8
  fcvtau x3, s8
  fcvtau x4, s8
  fcvtau x5, s8
  fcvtau x6, s8
  fcvtau x7, s8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa1a8c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1602044006229905772524010480100160004100160020500144013224002240041400411997761999216030020016003220016003240041400411180202100991008010010000111511701600400388000080000801004004240042400424004240042
160204400413000322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511701600400388000080000801004004240042400424004240042
160204400413000532524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511701600400388000080000801004004240042400424004240042
160204400413000322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511701600400388000080000801004004240042400424004240042
160204400412990322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000111516901600400388000080000801004004240042400424004240042
160204400413740322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511701600400388000080000801004004240042400424004240042
160204400413000322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511701600400388000080000801004004240042400424004240042
160204400413000322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511701600400388000080000801004004240042400424004240042
160204400412990322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511701600400388000080000801004004240042400424004240042
1602044004131118322524010480100160004100160020500144013214028240041400411997761999216012020016003220016003240041400411180201100991008010010000111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa6a8accfd2icache miss (d3)d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160024400553000042252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000050200015161714400388000080000800104004240042400424004240042
1600244004130000232252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000050200010161515400388000080000800104004240042400424004240042
160024400413220042252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000050200014161015400388000080000800104004240042400424004240042
160024400412990042252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000050200011161212400388000080000800104004240042400424004240042
160024400413000042252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000050200016161512400388000080000800104004240042400424004240042
160024400412990063252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000050200013161310400388000080000800104004240042400424004240042
160024400413000042252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000050200015161512400388000080000800104004240042400424004240042
160024400412990042252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000050200016161217400388000080000800104004240042400424004240042
160024400413070042252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000050200013161116400388000080000800104004240042400424004240042
160024400413000042252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000050200016161516400388000080000800104004240130400424004240042