Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTL (vector, 4S)

Test 1: uops

Code:

  fcvtl v0.4s, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l1i tlb fill (04)181e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037221090612547251000100010003981603018303730372414328951000100010003037303711100110000073316112629100030383038303830383038
100430372201006125472510001000100039816030183037303724143289510001000100030373037111001100001873116112629100030383038303830383038
100430372300006762547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037230000612547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037220000612547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037230090612547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372300001032547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037240000612547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037290000612547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037220000612547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtl v0.4s, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372320000000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000003071011611296330100001003003830038300383003830038
10204300372330000000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
102043003723200000005002954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296660100001003003830038300383003830038
10204300372330000000469295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000102071011611296330100001003003830038300383003830038
10204300372330000000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000106071011611296330100001003003830038300383003830038
10204300372330000300612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000103071011611296330100001003003830038300383008130038
102043003723200000006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000021071011611296330100001003003830038300383003830038
10204300372330000000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000002831071011612296330100001003003830038300383003830038
10204300372320000000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000003071011611296330100001003003830038300383003830038
102043003723300000001422954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000006071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037242000006832952054100101310008121000050428256803001830084300372828632878710460201032422100003008530037211002110910101000010000001373006402162229629010000103003830038300383003830038
1002430037233000120612954725100101010000101000050427716003001830037300372828632876710010201016220100003003730037111002110910101000010000039406402162329629010000103003830038300383003830038
100243003724100012021512954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010020003006402162229629010000103003830038300383003830038
10024300372410000012429547251001010100001210150504277160030018301803003728286192876710010201000020100003003730037111002110910101000010000002840006402162329629010000103003830038300383003830038
10024300372320001770612954725100101410005101000050428106903001830084300372828632876710161201000020100123017930037111002110910101000010000000006402162329629010000103003830038300383003830038
100243003724100000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000003006402162229629010000103003830038301803003830083
10024300372410009072629547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000024016402162229686010000103003830038300383003830038
100243008424100000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000009006402162229629010000103003830132300383003830038
10024300372421000027652954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000009007272162229629010000103003830038300383003830038
100243003724300000582429475192100841810072151120081428932813034230464304172831641289371127328114613611444304163046110110021109101010000100220124945008503973229986310000103050730507305123051030511

Test 3: throughput

Count: 8

Code:

  fcvtl v0.4s, v8.4h
  fcvtl v1.4s, v8.4h
  fcvtl v2.4s, v8.4h
  fcvtl v3.4s, v8.4h
  fcvtl v4.4s, v8.4h
  fcvtl v5.4s, v8.4h
  fcvtl v6.4s, v8.4h
  fcvtl v7.4s, v8.4h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005915500005052580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180161020036800001002004020040200402004020040
80204200391550000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000311151180160020036800001002004020040200402004020040
80204200391550000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
80204200391600000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
80204200391560000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000001011151180160020036800001002004020040200402004020040
80204200391550000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
80204200391550000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
80204200391550000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000003011151180160020036800001002004020040200402004020040
80204200391550000302580108100800081008012850064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000003011151180160020036800001002004020040200402004020040
80204200391560000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000311151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915504025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000502031602420036180000102004020040200402004020040
800242003915508225800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000502031602620036080000102004020040200402004020040
800242003915604025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001001000502031605320036080000102004020040200402004020040
8002420039155124025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001001000502051603620036080000102004020040200402004020040
800242003915604025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000502031605620036080000102004020040200402004020040
800242003915504025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001007000502031603220036080000102004020040200402004020040
8002420039155040258001010800001080000506400000200202003920039100113100198001020800002080000200392003911800211091010800001000000502031602320036080000102004020040200402004020040
800242003915504025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000502061603320036080000102004020040200402004020040
800242003915504025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800221091010800001000000502061603220036080000102004020040200402004020040
800242003915504025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000502031606620036080000102004020040200402004020040