Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTMS (scalar, D to D)

Test 1: uops

Code:

  fcvtms d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303724003612547251000100010003981603018303730372414328951000100010003037303711100110000073216112629100030383038303830383038
100430372300282612547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723000612547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723000612547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723000612547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037240001032547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723000612547251000100010003981603018303730372414328951000100010003037303711100110001073116112629100030383038303830383038
1004303723000612547251000100010003981603018303730372414328951000100010003037303711100110001073116112629100030383038303830383038
1004303724000822547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303724000612547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtms d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372330000008429547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000040071611611296330100001003003830038300383003830038
10204300372330000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830134
10204300372330000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
10204300372330000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100001100071011611296330100001003003830038300383003830038
102043003723300000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000001012071011611296330100001003003830038300383003830038
10204300372330000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000100071011612296640100001003003830038300383003830038
1020430037233000054006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
10204300372330000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010167300373003711102011009910010010000100000000071011611296780100001003003830038300383003830038
10204300372330000306129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000103071011611296330100001003003830038300383003830038
1020430229232010103528929547251011910010000100100005004277160130018300373003728264328762101002101000023210662304163003711102011009910010010000100000001126111011193233010235100001003059730709306583066130613

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243008522500001242954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629110000103003830038300383003830038
10024300372250000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010200006402162229629010000103003830038300383003830038
100243003722400001032954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722501200612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
10024300372250000612954725100101010000121000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
10024300372250000612954725100101010000101000050428256813001830037300372828632876710010201000020100003022730037111002110910101000010000006402162229629010000103003830038300383003830038
10024300372250000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
10024300372250000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
10024300372250000612954725100101010000101000050427716013001830037302242828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
10024300372250000612954725100281010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtms d0, d8
  fcvtms d1, d8
  fcvtms d2, d8
  fcvtms d3, d8
  fcvtms d4, d8
  fcvtms d5, d8
  fcvtms d6, d8
  fcvtms d7, d8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)fetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200611550302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000003111511816020036800001002004020040200402004020040
80204200391560302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511816020036800001002004020040200402004020040
80204200391550302580108100800081008002050064078812002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511816020036800001002004020040200402004020040
80204200391550302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511816020036800001002004020040200402004020040
80204200391550582580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511816020036800001002004020040200402004020040
80204200391550302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511816020036800001002004020040200402004020040
80204200391563302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511816020036800001002004020040200402004020040
80204200391550722580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511816020036800001002004020040200402004020040
80204200391556302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511816020036800001002004020040200402004020040
80204200391553302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000100111511816020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915500004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000502019161311200360080000102004020040200402004020040
800242003915500004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001040000502011161211200360080000102004020040200402004020040
80024200491560000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000050201116129200360080000102004020040200402004020040
800242003916100004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000502012161213200360080000102004020040200402004020040
800242003915500004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000502013161311200360080000102004020040200402004020040
800242003915500004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000502011161113200360080000102004020040200402004020040
800242003915500004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001001000502013161212200360080000102004020040200402004020040
800242003915600004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000060502011161111200360080000102004020040200402004020040
800242003915500004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000502013161414200360080000102004020040200402004020040
800242003915500004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000502013161212200360080000102004020040200402004020040