Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTMS (scalar, D to W)

Test 1: uops

Code:

  fcvtms w0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541504325300010002000200018000052254154124832742000200020005415411110011000037311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541464325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541504325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtms w0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0307080a0b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8a9acc5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30204130038974101000001130023119474254010010100200001000010020000100005006214979148010340130013013003813003812548361262423010020010002200062001000220006130038130038112020110099100101001000010000100000000111131702162212953710000100001000010100130039130039130039130039130039
302041300389741010000011300231194582540100101002000010000100200001000050062149791480103401300130130038130074125487312624630100200100002000020010000200001300381300381120201100991001010010000100001000003000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000000130034119492254010010100200001000010020000100005006214979148010340130013013004213003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000000130023119474254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000000131012162212952510003100001000010100130039130039130039130039130039
30204130038974000000000130023119472254010010100200001000010020000100005006214979148010340130013013003813003812550531262463010020010000200002001000020000130038130038112020110099100101001000010000100000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000000130023119441254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000100000131012162212952510000100001000010100130039130039130108130039130039
30204130038974000000000130023119435254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000000131012162312952510000100001000010100130039130039130039130100130039
30204130038974000000000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038212020110099100101001000010000100000000000131012162212952510000100001000010100130039130039130097130046130039
30204130040974000000000130023119419254010010100200001000010020000100005006214979148010340130013013003813003812547631262493010020010000200002001000020000130038130038112020110099100101001000010000100000000000131012162212952510000100001000010100130039130039130142130039130042
30204130038974000000000130023119440254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000000131012162212952510000100001000010100130039130039130039130064130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0308090b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a2a6a7a8acbranch mispredict (cb)cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038100800000420130023119417324001010010200001000010200001000050621497914800025013001313003813003812550831262683001020100002000020100002000013003813003811200211091010010100001000010000000012701161112952510000100001000010010130039130039130039130070130039
3002413003810080000000130023119417254001010010200001000010200001000050621497914800025013001313003813003812554631262683001020100002000020100002000013003813003811200211091010010100001000010000000012701161112952510000100001000010010130039130039130039130039130039
3002413003810080000000130023119417254001010010200001000010200001000050621512314800025013001313003813003812555531262683001020100002000020100002000013003813003811200211091010010100001000010000000012701161212952510000100001000010010130039130039130039130039130039
3002413003810080000000130039119417254001010010200001000010200001000050621497914800025013001313003813003812554731262683001020100622000020100002000013003813003811200211091010010100001000010000000012701161112952510000100001000010010130039130039130039130039130039
30024130038974000000013002311941725400101001020000100001020000100005062149791480002501300131300381300381255413126268300102010000200002010000200001300381300381120021109101001010000100001000032380012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000001300231194172540010100102000010000102000010000506214979148000250130013130038130038125554312626830010201000020000201000020000130038130038112002110910100101000010000100000680012701161112952510000100001000010010130039130039130039130039130039
300241300389740000000130049119417254001010010200001000010200001000050621497914800025013001313003813003812551231262683001020100002000020100002000013003813003811200211091010010100001000010000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025113001313003813003812554231262683001020100002000020100002000013003813003811200211091010010100001000010000003012701161112952510000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025013001313003813003812553431262683001020100622000020100002000013003813003811200211091010010100001000010000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025013001313003813010812549831262683001020100002000020100002000013003813010511200211091010010100001000010000003012701161112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtms w0, d8
  fcvtms w1, d8
  fcvtms w2, d8
  fcvtms w3, d8
  fcvtms w4, d8
  fcvtms w5, d8
  fcvtms w6, d8
  fcvtms w7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9facc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400662990322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001003111511701600400388000080000801004004240042400424004240042
160204400413000322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511701600400388000080000801004004240042400424004240042
1602044004130008612524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511701600400388000080000801004004240042400424004240042
160204400413000532524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511701600400388000080000801004004240042400424004240042
160204400412990322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511701600400388000080000801004004240042400424004240042
160204400412990322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511701600400388000080000801004004240042400424004240042
160204400413000322524010480182160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511701600400388000080000801004004240042400424004240042
160204400413000322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511701610400388000080000801004004240042400424004240042
160204400413000322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511701600400388000080000801004004240042400424004240042
160204400413000322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03080b18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a6a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244004230000000042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000005020316224003880000080000800104004240042400424004240042
16002440041300000000707252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000005020216224003880000080000800104004240042400424004240042
1600244004130000000042252400108001016000010160000501440000040022400414004119996320195160010201600002016000040041400411180021109108001010000005020216224003880000080000800104004240042400424004240042
1600244004130000000042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000005020216224003880000080000800104004240042400424004240042
1600244004130000000042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000065020216224003880000080000800104004240042400424004240042
1600244004130000000042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000005020216224003880000080000800104004240042400424004240042
1600244004130000000042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000005020216224003880000080000800104004240042400424004240042
16002440041300000000196252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000035020216224003880000080000800104004240042400424004240042
160024400413000000267042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000005020216224003880000080000800104004240042400424004240042
160024400413000000558042252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010000005020216224003880000080000800104004240042400424004240042