Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTMS (scalar, D to X)

Test 1: uops

Code:

  fcvtms x0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
20045414043253000100020002000180000522541541248327420002000200054154111100110007331633538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110007331633538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110007331633538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110007331633538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110007331633538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110007331633538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110007331633538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110007331633538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110007331633538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110007331633538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtms x0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0304181e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acbranch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300389741000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312629330100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312629930100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130102130043130039
302041300429740000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312628730100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126294301002001000020000200100002012913003813003811202011009910010100100001002010000021881000131012162212952510000100001000010100130039130622130597130039130083
30204130038974030013002311941725401001010020000100001002000010000500621497914801034113001313003813003812547631263023010020010000200002001000020000130038130038112020110099100101001000010000100000020100131012163212952510000100001000010100130039130039130039130039130039
302041300389740000130023119417254010010100200041000010020000100005006214979148010341130013130038130038125476312625530100202100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000130023119417254010010100200001000010020000100005006214979148010340130013130038130038125476312626330100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312629230100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000130023119417254010010100200001000010020000100005006214979148010340130013130038130038125476312627630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000130058119417254010010100200001000110020000100005006214979148010341130013130038130038125476312627330100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212955710000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0307080a18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)7a~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a7a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
300241300381008000000013002811941725400101001020000100001020000100005062149791480002501300133130038130038125498312626830010020100002000020100002000013003813003811200211091010010100001001000000012702161112952510000100001000010010130039130039130039130039130039
300241300381008000000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010020100002000020100002000013003813003811200211091010010100001001000000012701161112952610000100001000010010130039130039130039130039130039
300241300381007000000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010020100002000020100002000013003813003811200211091010010100001001000000012701161112952510000100001000010010130039130039130039130039130039
300241300381008000000013002311941825400101001020000100001020000100005062149791480002511300130130038130038125498312626830010020100002000020104312097513073813080991200211091010010100001001000510012701161112952510000100001000010010130039130039130039130039130039
300241300381007000000013002311941725400101001020000100001020000100005062149791480002511300130130038130038125498312626830010020100002000020100002000013003813003811200211091010010100001001000000012701161112952510000100001000010010130039130039130039130039130039
300241300381008000000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010020100002000020100002000013003813003811200211091010010100001001000000012701161112952510000100001000010010130039130039130039130039130039
300241300381008000000013002311941725400101001020000100001020000100005062149791480002511300130130038130038125498312626830010020100002000020100002000013003813003811200211091010010100001001000000012701161112952510000100001000010010130039130039130039130039130039
3002413003810080000030013002311941725400101001020000100001020000100005062149791480002501300130130038130038125512312626830010020100002000020100002000013003813003811200211091010010100001001000000012701161112952510000100001000010010130039130039130039130039130039
300241300381008000000013002411941725400101001420000100001020000100005062149791480002511300130130038130038125498312626830010020100002000020100002000013003813003811200211091010010100001001000000012701161112952510000100001000010010130039130075130085130039130039
30025130081974000000013002311941725400101001020000100001020000100005062149791480002511300130130038130038125498312626830010020100002000020100002000013003813003811200211091010010100001001000001012701161112952510000100001000010010130039130039130039130039130040

Test 3: throughput

Count: 8

Code:

  fcvtms x0, d8
  fcvtms x1, d8
  fcvtms x2, d8
  fcvtms x3, d8
  fcvtms x4, d8
  fcvtms x5, d8
  fcvtms x6, d8
  fcvtms x7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030b181e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16020440062300000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511701600400388000080000801004004240042400424004240042
160204400413000005325240104801001600041001600205001440132140022400414004119977151999216033620016003220016003240041400411180201100991008010010000111511701600400388000080000801004004240042400424004240042
160204400413000006022524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511701600400388000080000801004004240042400424004240042
160204400412990005982524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511711600400388000080000801004004240042400424004240042
16020440041300000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511701600400388000080000801004004240042400424004240042
16020440041300000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511701600400388000080000801004004240042400424004240042
16020440041300000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511701600400388000080000801004004240042400424004240042
16020440041300000322524035080100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511701600400388000080000801004004240042400424004240042
16020440041300000322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511701600400388000080000801004004240042400424004240042
16020440041300000322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030718191e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a8a9acc2branch mispredict (cb)cfd0d5d6dbddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160024400553000000013012524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000000050200216055400388000080000800104004240042400424004240042
16002440041300000000422524001080010160000101600005014400001040022040041400411999632002116001020160000201600004004140041118002110910800101000000050200316034400388000080000800104004240042400424004240042
160024400413000000002352524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000000050200416043400388000080000800104004240042400424004240042
160024400413000000001952524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000000050200316044400388000080000800104004240042400424004240042
160024400413000000001282524001080010160180101600005014400000040022040041400411999632002116001020160000201600004004140041118002210910800101000000050200416043400388029280000800104004240042400424004240042
160024400413000000009202524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000000050200316044400388000080000800104004240042400424004240042
160024400413000000001322524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000000050200416044400388000080000800104004240042400424004240042
160024400413000009001072524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000000050200516035400388000080000800104004240042400424004240042
160024400413000000001952524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000030050200416044400388000080000800104004240042400424004240042
160024400412990000003212524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000000050200316033400388000080000800104004240042400424004240042