Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTMS (scalar, H to H)

Test 1: uops

Code:

  fcvtms h0, h0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372400612547251000100010003981600301830373037241432895100010001000303730371110011000073216112629100030383038303830383038
100430372300612547251000100010003981600301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
1004303723006542547251000100010003981600301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
100430372400612547251000100010003981600301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
100430372300612547251000100010003981600301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
100430372300612547251000100010003981600301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
100430372300612547251000100010003981600301830373037241432895100010001000303730371110011000273116112629100030383038303830383038
1004303724001022547251000100010003981600301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
100430372400612547251000100010003981600301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
1004303724004762547251000100010003981600301830373037241432895100010001000303730371110011000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtms h0, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723306129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000710116112963300100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000710116112963300100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000710116112963300100001003003830038300383003830038
1020430037232011429547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100100710116112963300100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000710116112963300100001003023430038300383003830038
1020430037233126129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000710116112963300100001003003830038300383003830038
102043003723206129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000710116112963300100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100001710116112963300100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100100710116112963300100001003003830038300383003830038
1020430037233010329547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000710116112963300100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000101006402162229629010000103003830038300383003830038
100243003722400006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000101006402162229629010000103003830038300383003830038
100243003722500006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000101036402162229629010000103003830038300383003830038
100243003722500006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
100243003722500006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
100243003722500006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000103006402162229629010000103008130038300383003830038
100243003722500006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
100243003722500006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100006404164129701310000103013130132300853008530133
1002430131226000061295472510010101000010103005042771601300183003730084282863287671001020101622010000300373003711100211091010100001034406404242229629010000103003830038300383003830038
1002430084225131220811205295479010061101000010100005042771601303063041730367283062728877100102211301221130930309304189110021109101010000101006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtms h0, h8
  fcvtms h1, h8
  fcvtms h2, h8
  fcvtms h3, h8
  fcvtms h4, h8
  fcvtms h5, h8
  fcvtms h6, h8
  fcvtms h7, h8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042004915503025801081008000810080020500640132120020020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040200402004020040
802042003915503025801081008000810080020500640132020020020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040201972009120040
80204200391552731125801081008000810080020500640132020020020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040200402004020040
802042003915503025801081008000810080020500640132020020020039200399977699908012020080032200800322003920039118020110099100100800001001011151181620036800001002004020040200402004020040
802042003915593025801081008000810080020500640132020020020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040200402004020040
802042003915603025801081008000810080020500640132020020020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040200402004020040
802042003915503025801081008000810080020500640132020020020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040200402004020040
802042003915503025801081008000810080020500640132020020020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040200402004020040
802042003915598425801081008000810080020500640132020020020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040200402004020040
802042003915503025801081008000810080020500640132020020020039200399977699908012020080032200800322003920039118020110099100100800001000011151181620036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acl1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005015600000040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000000050201216352003680000102004020040200402004020040
80024200391550000004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000005020416642003680000102004020040200402004020040
80024200391560000004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000003005020416532003680000102004020040200402004020040
8002420039156000000402580010108000010800005064000002002020039200399996310019801082080103208010420105200902180021109101080000100207525005055452662012880000102009420090201442010320103
800242008915610000031425800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000005020416532003680000102004020040200402004020040
80025200391550000004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000005020316642003680000102004020040200402004020040
800242003915600000040258001010800001080000506400000200202003920039100053100198001020800002080000200392003911800211091010800001000000005020516372003680000102004020040200402004020040
80024200391550000004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000005020516662003680000102004020040200402004020040
800242003915600000040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010001000050205163132003680000102004020040200402004020040
80024200391550000004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000005020416652003680000102004020040200402004020040