Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTMS (scalar, H to W)

Test 1: uops

Code:

  fcvtms w0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
20045413643253000100020002000180001522541541248327420002000200054154111100110007321622538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110007321622538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110007321622538100010001000542542542542542
20045414643253000100020002000180000522541541248327420002000200054154111100110007321622538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110007321622538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110007321622538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110007321622538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110007321622538100010001000542542542542542
200454141843253000100020002000180001522541541248327420002000200054154111100110007321622538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110007321622538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtms w0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8a9acc2c5cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3020413003897400013002311949625401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130081
3020413003897400013002311941725401331010020000100081232081110343597623778214856101113001313037713037912584531262923010020010000201222001000020122130038130038212020110099100101001000010010000300000131012162212952510000100001000010100130040130039130039130039130039
3020413003897403388130023119417254010010100200001000010020000100005006214979148013701130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100100103412903000131012162212952510000100001000010100130042130039130039130039130039
3020413003897400013002311945065401001010020000100001002000010000500621497914801148113001413004213003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130045130039130039130039130110
3020413003897400013002311941725401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
3020513003897400013002311941725401001010020000100021002011610000500621497914801034113001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000132512162212952510019100001000010100130039130039130039130039130039
30204130038974112013002311941725401001010020000100001002000010000500621497914801034113001313003813003812547631262473010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100100073000000131012162212952510000100001000010100130039130070130039130039130039
3020413003897400013005711942125401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400013002311941725401001010020000100001002000010000500621497914801034113001313003813003812547631262673010020010000200002001000020000130038130038112020210099100101001000010010000000010131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030818191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8acc2c5cficache miss (d3)d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038974000901300301194172540010100102000010000102000010000506214979148000251300150130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000016500127001161112952510000100001000010010130039130039130039130039130039
300241300389741000013002311941725400101001020000100001020000100005062149791480002513001301300381300381254983126268300102010000200002010000200001300391300421120021109101001010000100100000000127001161112952510000100001000010010130039130039130039130039130039
30024130103973000001300231194172540010100102000010000102000010000506214979148000251300130130038130039125528312626830010201000020000201000020000130038130038112002110910100101000010010000116000127001161112952510000100001000010010130044130039130039130039130039
300241300389740000013002311941725400101001020000100001020000100005062149791480002513001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000127002161112952510000100001000010010130039130039130039130039130039
300241300389730000013002311942125400101001020000100011020000100005062342241480002513001301300381300381257903126794300102010000200002010000203591300381300381120021109101001010000102100000000127001161112952510000100001000010010130039130042130039130039130039
3002413003897400000130023119493254001010010200001000010200001000050621497914800025130013013003813003812549831262683001020100002000020100002000013007913004711200211091010010100001001000001500127001161112952510000100001000010010130039130039130039130039130039
3002413003897400000130023119520254001010010200001000010200001000050621497914800025130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000079000127001171112952510000100001000010010130039130039130039130039130039
300241300389740000013002311941725400101001020000100001020000100005062149791480002513001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000127001161112952510000100001000010010130039130039130039130039130039
300241300389740000013002311941725400101001020000100001020000100005062149791480002513001301300381300381254983126268300102010000200002010000200001300381300741120021109101001010000100100000000127001161112952510000100001000010010130039130039130039130039130039
300241300389740000013002311941725400101001020000100001020000100005062149791480002513001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000127002161112958710000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtms w0, h8
  fcvtms w1, h8
  fcvtms w2, h8
  fcvtms w3, h8
  fcvtms w4, h8
  fcvtms w5, h8
  fcvtms w6, h8
  fcvtms w7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03080918191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa6a8a9acc2c5branch mispredict (cb)cdcfd5d6dde0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1602044005330002000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000011151172160400388000080000801004004240042400424004240042
1602044004130000000032252401048010016000410016002050014401320400834004140041199776199921601202001602482001600324004140041118020110099100801001000040011151170160400388000080000801004004240042400424004240042
1602044004130000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000100011151170160400388000080000801004004240042400424004240042
1602044004130000000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000011151170160400388000080000801004004240042400424004240042
1602044004130000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000011151170160400388000080000801004004240042400424004240042
1602044004129900006032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324011940277118020110099100801001000000011151170160400388000080000801004004240042400424004240042
1602044004130000000032252401048010016000410016002050014401320400864004140041199776199921601202001600322001600324004140041118020110099100801001000000011151170160400388000080000801004004240042400424004240042
1602044004129900000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000011151170160400388000080000801004004240042400424004240042
1602044004130000000055252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000011151170160400388000080000801004004240042400424004240042
1602044004130000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000011151170160400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)6061696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a6a8a9acc5cfd0d2d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005530007072524001080010160000101600005014400001040022400414004119996320021160010201600002016000040041400411180021109108001010000000050205061654400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400000540022400414004119996320021160010201600002016000040041400411180021109108001010000000050205051645400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400000540022400414004119996320021160010201600002016000040041400411180021109108001010000000050205251664400388000080000800104004240042400424004240042
160024400412990422524001080010160000101600005014400001040022400414004119996320080160010201600002016000040041400411180021109108001010000000050205271667400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400001540022400414004119996320021160010201600002016000040041400411180021109108001010000000050375261654400388000080000800104004240042400424004240042
160024400412990422524001080010160000101600005014400001540022400414004119996320021160010201600002016000040041400411180021109108001010000000050205261655400388000080000800104004240042400424004240042
160024400413140422524001080010160000101600005014400001540022400414004119996320021160010201600002016000040041400411180021109108001010000200050205261666400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400001540022400414004119996320021160010201600002016000040041400411180021109108001010000100050205251665400388000080000800104004240042400424004240042
1600244004130018422524001080010160000101600005014400001540022400414004119996320021160010201600002016000040041400411180021109108001010000000050208251666400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400001540022400414004119996320021160010201600002016000040041400411180021109108001010000000050205251656400388000080000800104004240042400424004240042