Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTMS (scalar, H to X)

Test 1: uops

Code:

  fcvtms x0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a1a8cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtms x0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)031e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8acc2c5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300389740130023119417254010010100200001000010020000100005006214979148010341130048130038130038125483712624130100200100022000620010002200061300381300801120201100991001010010000100010000000111131801161412962410000100001000010100130039130039130039130039130039
302041300389740130023119417254010010100200001000010020000100005006214979148010341130013130044130038125483612624230100200100022000620010002200061300381300381120201100991001010010000100010000000111131801161112953310000100001000010100130039130039130039130039130039
302041300419740130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131002162212959010000100001000010100130078130039130039130039130061
3020413003897421130053119417254010010100200001000110020000100005006214979148010341130013130038130038125476312624630100200100002000020010067200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740130023119417254010010100200001000010020000100005006214979148010341130013130038130041125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162312952510000100001000010100130071130039130039130039130039
302041300389740130023119423254010010104200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381301151120201100991001010010000100010000100000131012162212952510000100001000010100130039130039130039130039130039
30204130038974639130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381301051120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740130023119417254010010100200001000010020000100005006215267148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000030000131012162212952510000100001000010100130039130039130039130208130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8acc5cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038973000000130023119449254001010010200001000010200001000050621497914800025113001301300381300381254983126279300102010000200002010000200001300381300381120021109101001010000101000000012702160312952510000100001000010010130039130039130039130110130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025113001601300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130039130102130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300391120021109101001010000101000000012701161112956610000100001000010010130039130039130083130068130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025113001301300431300381254983126268300102010000201312010000200001300751300441120021109101001010000101000000012701161212952510000100001000010010130039130039130039130095130040
30024130038974000000130023119417254003710010200001000010200001000061621497914800025113009201300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130081130070130039
30024130038974000000130023119421254001010010200001000010200001000050621525314805128113001331300381300381254983126268300102010000200002010066200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130039130122130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130039130107130039
30024130038974000000130023119452254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161212952510000100001000010010130039130039130080130063130039
30024130038974000000130023119437254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130039130121130039
30024130038974000000130023119547254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130091130051130039

Test 3: throughput

Count: 8

Code:

  fcvtms x0, h8
  fcvtms x1, h8
  fcvtms x2, h8
  fcvtms x3, h8
  fcvtms x4, h8
  fcvtms x5, h8
  fcvtms x6, h8
  fcvtms x7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03070a1e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16020440041311110322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041401261180201100991008010010010111511731623400388000080000801004004240042400424004240042
160204400413221102222524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511731632400388000080000801004004240042400424004240042
160204400413111108862524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511721633400388000080000801004004240042400424004240042
16020440041310110322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511731633400388000080000801004004240042400424004240042
16020440041310110322524010480100160208100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511731633400388000080000801004004240042400424004240042
16020440041310110322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511721623400388000080000801004004240042400424004240042
16020440041310110322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511721623400388000080000801004004240042400424004240042
16020440041310110322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511721623400388000080000801004004240042400424004240042
16020440041311110322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511731623400388000080000801004004240042400424004240042
160204400413101106972524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511731633400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8a9acc2c5cfd0d2d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005431012422524001080010160000101600005014400004002204004140041199963200211600102016000020160000400414004111800211091080010100000050200017161617400388000080000800104004240042400424004240042
16002440041311042252400108001016000010160000501440000400220400414004119996320021160010201600002016000040041400411180021109108001010110005020001616166400388000080000800104004240042400424004240042
1600244004131004225240010800101600001016000050144000040022040041400411999632002116001020160000201600004004140041118002110910800101000000502000616616400388000080000800104004240042400424004240042
1600244004131104225240010800101600001016000050144000040022040041400411999632002116001020160000201600004004140041118002110910800101000000502000616166400388000080000800104004240042400424004240042
160024400413100422524001080010160000101600005014400004002204004140041199963200211600102016000020160000400414004111800211091080010100000050200016161616400388000080000800104004240042400424004240042
1600244004131004225240010800101600001016000050144000040022040041400411999632002116001020160000201600004004140041118002110910800101000000502000616176400388000080000800104004240042400424004240042
16002440041310042252400108001016000010160000501440000400220400414004119996320021160010201600002016000040041400411180021109108001010000005020001616166400388000080000800104004240042400424004240125
1600244004131004225240010800101600001016000050144000040022040041400411999632002116001020160000201600004004140041118002110910800101000000502000616166400388000080000800104004240042400424004240042
1600244004131104225240010800101600001016000050144000040022040041400411999632002116001020160000201600004004140041118002110910800101000000502000616166400388000080000800104004240042400424004240042
160024400413113370725240010800101600001016000050144000040022040041400411999632002116001020160000201600004004140041118002110910800101000000502000616166400388000080000800104004240042400424004240042