Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTMS (scalar, S to S)

Test 1: uops

Code:

  fcvtms s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230006125472510001000100039816003018303730372414328951000100010003037303711100110003073116112629100030383038303830383038
100430372300061254725100010001000398160030183037303724143289510001000100030373037111001100003073116112629100030383038303830383038
10043037230006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037241006125472510001000100039816013018303730372414328951000100010003037303711100110002073116112629100030383038303830383038
100430372301061254725100010001000398160030183037303724143289510001000100030373037111001100001273116112629100030383038303830383038
10043037230006125472510001000100039816003018303730372414328951000100010003037303711100110000373116112629100030383038303830383038
10043037230006125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037230006125472510001000100039816003018303730372414328951000100010003037303711100110001073116112629100030383038303830383038
10043037240066125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037230006125472510001000100039816003018303730372414328951000100010003037303711100110002073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtms s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723300007312954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
102043008423300001052954725101001001000010010000500427716003001803007630037282643287451010020010000200100003003730037111020110099100100100001002007101161129633100001003003830038300383003830038
1020430037234112007262954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
102043003723300001242954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
102043003723200001032954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
102043003723300002752954725101001251001610010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000007104161129633100001003003830038300383003830038
10204300372330000612954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000037101161129633100001003003830038300383003830038
102043003723300001032954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000007101161229633100001003003830038300383003830038
10204300372330000822954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000207101161129633100001003003830038300383003830038
10204300372330000612954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000007101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037233904702954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006403163329629010000103003830038300383003830038
10024300372321501052954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010006403163329629010000103003830038300383003830038
100243003723200612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010006403163329629010000103003830038300383003830038
100243003723300612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010006403163329629010000103003830038300383003830038
1002430037233006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000101406403163329629010000103003830038300383003830038
100243003723300612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010006403163329629010000103003830038300383003830038
100243003723300822954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010006403163329629010000103003830038300383003830038
100243003723300612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010006403163329629010000103003830038300383003830038
1002430037233002332954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010006403163329629310000103003830038300383003830038
1002430037233008582954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010106403163329629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtms s0, s8
  fcvtms s1, s8
  fcvtms s2, s8
  fcvtms s3, s8
  fcvtms s4, s8
  fcvtms s5, s8
  fcvtms s6, s8
  fcvtms s7, s8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420061155110302580108100800081008002050064013220020020039200399977699908012020080032200800322003920039118020110099100100800001000011151182161120036800001002004020040200402004020040
80204200391551112302580108100800081008002050064013220020020039200399977699908012020080032200800322003920039118020110099100100800001000011151181161120036800001002004020040200402004020040
80204200391551103512580108100800081008002050064013220020020039200399977699908012020080032200800322003920039118020110099100100800001000011151181161120036800001002004020040200402004020040
8020420039155110352580108100800081008002050064013220020020039200399977699908012020080032200800322003920039118020110099100100800001000611151181161120036800001002004020040200402004020040
8020420039156110302580108100800081008002050064013220020020039200399977699908012020080032200800322003920039118020110099100100800001000011151181161120036800001002004020040200402004020040
8020420039155110302580108100800081008002050064013220020020039200399977699908012020080032200800322003920039118020110099100100800001000011151181161120036800001002004020040200402004020040
8020420039155110302580108100800081008002050064013220020020039200399977699908012020080032200800322003920039118020110099100100800001000011151181161120036800001002004020040200402004020040
8020420039155110302580108100800081008002050064013220020020039200399977699908012020080032200800322003920039118020110099100100800001000011151181161120036800001002004020040200402004020040
8020420039156110722580108100800081008002050064013220020020039200399977699908012020080032200800322003920039118020110099100100800001000011151181161120036800001002004020040200402004020040
8020420039155110302580108100800081008002050064013220020020039200399977699908012020080032200800322003920039118020110099100100800001000011151181161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acl1d cache miss st nonspec (c0)c2cfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420051156000000004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000050201716813132019980000102004020040200402004020040
8002420039155000000004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000030050201716812132003680000102004020040200402004020040
8002420039155000000004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000050201616616122003680000102004020040200402004020040
80024200391550000000010325800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000050201416616132003680000102004020040200402004020040
80024200391550000012004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000030050201716612122003680000102004020040200402004020040
8002420039155000000004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000050201616614132003680000102004020040200402004020040
80024200391550000000014525800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000050201716618182003680000102004020040200402004020040
8002420039156000000008225800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000050201116612122003680000102004020040200402004020040
8002420039156000000004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000050201516017142003680000102004020040200402004020040
8002420039155000000004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000050201516017152003680000102004020040200402004020040