Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTMS (scalar, S to W)

Test 1: uops

Code:

  fcvtms w0, s0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)030b18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a1a6a8a9acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
200454140000043253000100020002000180001522541541248327420002000200054154111100110000000007331633538100010001000542542542542542
200454140000043253000100020002000180001522541541248327420002000200054154111100110000000007331633538100010001000542542542542542
200454140000043253000100020002000180001522541541248327420002000200054154111100110000000007331633538100010001000542542542542542
200454140000043253000100020002000180001522541541248327420002000200054154111100110000000007331633538100010001000542542542542542
200454140009043253000100020002000180001522541541248327420002000200054154111100110000000007331633538100010001000542542542542542
200454140000043253000100020002000180001522541541248327420002000200054154111100110000000007331633538100010001000542542542542542
200454150000043253000100020002000180001522541541248327420002000200054154111100110000000007331633538100010001000542542542542542
200454140000043253000100020002000180001522541541248327420002000200054154111100110000000007331633538100010001000542542542542542
200454140000043253000100020002000180001522541541248327420002000200054154111100110000010007331633538100010001000542542542542542
200454140000043253000100020002000180001522541541248327420002000200054154111100110000000007331633538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtms w0, s0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8a9acc5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300130130038130038125483712624230100200100022000620010002200061300381300381120201100991001010010000100010000000111131701161112953310000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000001131012162212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300130130038130038125476312624630100202100002000020010000200001300381300381120201100991001010010000100010000000000131013162212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300130130038130038125476312624630100200100002000020010000201281300391300411120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000013002311971421540161101352002710018124210421044158462375231485228711300130130038130039125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012171212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300130130040130041125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300130130038130038125476312624630100206100612000020010000200001300381300381120201100991001010010000100010000000000131012162212960310000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300160130041130038125476312624630100200100002000020010000200001300381300711120201100991001010010000100010000000000131013162212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194202540100101002000010000100200001000050062149791480103411300130130041130049125514312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0308090b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8acc2c5cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3002413003897400000001300231194762540010100102000010000102000010000506214979148000251300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000300012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000001300231194552540010100102000010008102000010000506214979148001391300131300401300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000002012701161112952510000100001000010010130039130039130039130039130039
3002413003897400030001300231194282540010100102000010000102000010000506214979148000251300131300381300381254983126268300102010000200002010000200001300381300425120021109101001010000100010000000012701161212952510000100001000010010130371130040130039130039130039
3002413003897400000901300231194582540010100102000010000102000010000506215123148000251300131300381300401256473126268300102010000200002010000200001300381300381120021109101001010000100010000000012701162112952510000100001000010010130039130039130039130039130039
30024130039975000400013002311947625400101001020000100001020000100005062149791480002513001313003813003812549831262683067320100002000020100002000013003813003811200211091010010100001000100000172720012701162112952510000100001000010010130040130040130388130039130039
30024130038974100003901303421194632540010100102000010000132000010000506214979148000251300141300381303771255623126268303392010000200002010000201221300381300381120021109101001010000100010000400112701161112952610000100001000010010130042130039130124130081130039
3002413003897400000601300231194182540018100102000010000102000010000506214979148001361300141300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000330012701161112952710000100001000010010130039130039130039130039130039
300241300389740000066881300231194772540010100102000010000102000010000506214979148003701300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952510000100001000010010130039130042130039130109130039
3002413003897400000001300231194882540010100102000010000102000010000506214979148000251300131300381300381254983126268300102010000200002010000200001300381300681120021109101001010000100010000000012702161112952610000100001000010010130039130039130039130039130039
3002413003897400000001300231194562540010100102000010000102000010049506214979148000251300141300381300381254983126325300102010000200002010000200001300481300381120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130114130039

Test 3: throughput

Count: 8

Code:

  fcvtms w0, s8
  fcvtms w1, s8
  fcvtms w2, s8
  fcvtms w3, s8
  fcvtms w4, s8
  fcvtms w5, s8
  fcvtms w6, s8
  fcvtms w7, s8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030818191e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a8acc5branch mispredict (cb)cdcfd6dde0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400643100000007425240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000011151171604003880000080000801004004240042400424004240042
160204400413100000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100001311151171604003880000080000801004004240042400424004240042
160204400413110000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000011151171604003880000080000801004004240042400424004240042
160204400413100000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000011151171604003880000080000801004004240042400424004240042
160204400413100000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414012021802011009910080100100000011151171604003880000080000801004004240042400424004240042
160204400413100000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000011151171604003880000080000801004004240042400424004240042
160204400413100000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000011151171604003880000080000801004004240042400424004240042
1602044004131000000017229240116801041600121001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000011151171604003880000080000801004004240042400424004240042
160204400413100003003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000011151171604003880000080000801004004240042400424004240042
160204400413100000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100001011151171704003880000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0307080a18191e1f203a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a6a8acatomic or exclusive success (b3)c2cfd5d6dadbddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005531100000000042252400108001016000010160000501440000014002204004140041199963200211600102016000020160000400414004111800211091080010100000005020181600613400388000080000800104004240042400424004240042
1600244004131000000000042252400108001016000010160000501440000014002204004140041199963200211600102016000020160000400414004111800211091080010100000005020161600166400388000080000800104004240042400424004240042
1600244004131000000000042252400108001016000010160000501440000014002204004140041199963200211600102016000020160000400414004111800211091080010100010005020161600166400388000080000800104004240042400424004240042
160024400413100000000007072524001080010160000101600005014400000140022040041400411999611200211600102016000020160000400414004111800211091080010100000005020161600166400388000080000800104004240042400424004240042
1600244004131000000000042252400108001016000010160000501440000014002204004140041199963200211600102016000020160000400414004111800211091080010100000005020161600166400388000080000800104004240042400424004240042
1600244004131000000000042252400108001016000010160000501440000014002204004140041199963200211600102016000020160000400414004111800211091080010100000005020161600616400388000080000800104004240042400424004240042
16002440041310000000000681252400108001016000010160000501440000014002204004140041199963200211600102016000020160000400414004111800211091080010100000005020616001616400388000080000800104004240042400424004240042
1600244004131100000000015525240010800101600001016000050144000001400220400414004119996320021160010201600002016000040041400411180021109108001010000000502061600616400388000080000800104004240042400424004240042
1600244004130000000000042252400108001016000010160000501440000014002204004140041199963200211600102016000020160000400414004111800211091080010100000005020161600166400388000080000800104004240042400424004240042
1600244004130000000000042252400108001016000010160000501440000014002204004140041199963200211600102016000020160000400414004111800211091080010100000005020161600166400388000080000800104004240042400424004240042