Firestorm: FCVTMS (scalar, S to W) measurements

Code:

  fcvtms w0, s0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	73	3	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	73	3	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	73	3	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	73	3	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	9	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	73	3	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	73	3	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	5	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	73	3	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	73	3	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	1	0	0	0	73	3	16	3	3	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	73	3	16	3	3	538	1000	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtms w0, s0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	0	130038	130038	125483	7	126242	30100	200	10002	20006	200	10002	20006	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1	1	1	1317	0	1	16	1	1	129533	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	0	130038	130038	125476	3	126246	30100	202	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	3	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20128	130039	130041	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119714	215	40161	10135	20027	10018	124	21042	10441	584	6237523	14852287	1	130013	0	130038	130039	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	17	1	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	0	130040	130041	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	0	130038	130038	125476	3	126246	30100	206	10061	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129603	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130016	0	130041	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130071	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	3	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119420	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	0	130041	130049	125514	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130038	974	0	0	0	0	0	0	0	130023	119476	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	3	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	0	130023	119455	25	40010	10010	20000	10008	10	20000	10000	50	6214979	14800139	130013	130040	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	2	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	3	0	0	0	130023	119428	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130042	5	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	2	129525	10000	10000	10000	10010	130371	130040	130039	130039	130039
30024	130038	974	0	0	0	0	0	9	0	130023	119458	25	40010	10010	20000	10000	10	20000	10000	50	6215123	14800025	130013	130038	130040	125647	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	2	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130039	975	0	0	0	4	0	0	0	130023	119476	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	130013	130038	130038	125498	3	126268	30673	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	17272	0	0	1270	1	16	2	1	129525	10000	10000	10000	10010	130040	130040	130388	130039	130039
30024	130038	974	1	0	0	0	0	39	0	130342	119463	25	40010	10010	20000	10000	13	20000	10000	50	6214979	14800025	130014	130038	130377	125562	3	126268	30339	20	10000	20000	20	10000	20122	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	4	0	0	1	1270	1	16	1	1	129526	10000	10000	10000	10010	130042	130039	130124	130081	130039
30024	130038	974	0	0	0	0	0	6	0	130023	119418	25	40018	10010	20000	10000	10	20000	10000	50	6214979	14800136	130014	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	3	3	0	0	1270	1	16	1	1	129527	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	66	88	130023	119477	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800370	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130042	130039	130109	130039
30024	130038	974	0	0	0	0	0	0	0	130023	119488	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130068	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	2	16	1	1	129526	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	0	130023	119456	25	40010	10010	20000	10000	10	20000	10049	50	6214979	14800025	130014	130038	130038	125498	3	126325	30010	20	10000	20000	20	10000	20000	130048	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130114	130039

Test 3: throughput

Count: 8

Code:

  fcvtms w0, s8
  fcvtms w1, s8
  fcvtms w2, s8
  fcvtms w3, s8
  fcvtms w4, s8
  fcvtms w5, s8
  fcvtms w6, s8
  fcvtms w7, s8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40064	310	0	0	0	0	0	0	74	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	16	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	3	1	1	1	5117	16	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	16	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	16	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40120	2	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	16	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	16	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	16	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	0	172	29	240116	80104	160012	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	16	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	3	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	16	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	0	1	1	1	5117	17	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	18	19	1e	1f	20	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	atomic or exclusive succ (b3)	c2	cf	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40055	311	0	0	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	18	16	0	0	6	13	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	16	16	0	0	16	6	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	1	0	0	0	5020	16	16	0	0	16	6	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	0	0	0	0	707	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	0	40041	40041	19996	11	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	16	16	0	0	16	6	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	16	16	0	0	16	6	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	16	16	0	0	6	16	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	0	0	0	0	681	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	6	16	0	0	16	16	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	311	0	0	0	0	0	0	0	0	0	155	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	6	16	0	0	6	16	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	16	16	0	0	16	6	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	16	16	0	0	16	6	40038	80000	80000	80010	40042	40042	40042	40042	40042

FCVTMS (scalar, S to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations