Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTMU (scalar, D to W)

Test 1: uops

Code:

  fcvtmu w0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)03080b18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a0a1a6a8a9acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
20045415000000852530001000200020001800005225415412483274200020002000541541111001100000000007311611538100010001000542542542542542
20045414000000432530001000200020001800005225415412483274200020002000541541111001100000010007311611538100010001000542542542542542
20045414000000432530001000200020001800005225415412483274200020002000541541111001100000000007311611538100010001000542542542542542
20045414000000432530001000200020001800005225415412483274200020002000541541111001100000000007311611538100010001000542542542542542
20045414000000432530001000200020001800005225415412483274200020002000541541111001100000000007311611538100010001000542542542542542
20045414000000432530001000200020001800005225415412483274200020002000541541111001100000000007311611538100010001000542542542542542
20045414000000432530001000200020001800005225415412483274200020002000541541111001100000000007311611538100010001000542542542542542
20045414000000432530001000200020001800005225415412483274200020002000541541111001100000002327312511538100010001000542542542542542
2004541401100043253274100020002000180000562541541248330420002000200054154111100110002200043007311611538100010001000621542542578542
20045415000000432530001000200020001800005225415412483274200020002214541541111001100000000007311611538100010001000542542542542621

Test 2: Latency 1->2 roundtrip

Code:

  fcvtmu w0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03040b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8acc5cfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3020413003897410000013002311945325401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131013162212952510000100001000010100130039130039130039130039130039
3020413003897400000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012162212952510000100001000010100130039130039130039130039130039
3020513003897400000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038212020110099100101001000010000100000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012165212952910000100001000010100130039130039130039130039130039
3020413003897400000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000013010111941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100020000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012162212952510000100001000010100130039130039130039130083130039
3020413003897400000013002311941738401001010020000100001002000010000500621497914801703013001313003813011412547731262463026920010000200002001000020000130038130038112020110099100101001000010000100000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262623010020010067200002001000020000130038130038112020110099100101001000010000100000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000984013002311941725401001010020000100001002000010000500621497914801034013001313003813003812548231262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8acc5cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
300241300389740000013002311941725400101001020000100001020000100005062150751480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012704163312952510000100001000010010130039130039130039130039130039
3002413003897400001513002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000030012703163312952510000100001000010010130039130039130039130039130147
300241300389740000013002311941725400101001020000100001020000100005062154441480002501300131300391300381255683126268300102010000200002010000200001300381300381120021109101001010000101000000012703163412952510000100001000010010130039130039130039130039130039
300241300389740000013002311941725400101001020000100001020000100005062149791480002511300131300381300411255043126268300102010000200002010000200001300381300381120021109101001010000101000010012703163412952510000100001000010010130039130039130039130039130039
300241300389740000013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000020012703163312952510000100001000010010130039130039130039130039130041
300241300389740000013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012704163312952510000100001000010010130039130039130039130039130039
3002413004597400001213002311941725400101001020000100001020000100005062149791480002511300491300381300381254993126268300102010000200002010000200001300381300381120021109101001010000101000000012704163312952510000100001000010010130040130039130039130039130076
300241300389740000013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000010012703163312952510000100001000010010130039130039130039130039130039
300241300389740000013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000020012702163412952510000100001000010010130039130039130039130039130040
300241300389740000013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268301802010000200002010000200001300381300381120021109101001010000101000050012703163312952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtmu w0, d8
  fcvtmu w1, d8
  fcvtmu w2, d8
  fcvtmu w3, d8
  fcvtmu w4, d8
  fcvtmu w5, d8
  fcvtmu w6, d8
  fcvtmu w7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03080b181e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)6061696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa1a8acc2c5branch mispredict (cb)cdcfd0d2d5d6ddinst fetch restart (de)e0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16020440075310000000372524010480100160004100160020500144013200400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511700016004003880000080000801004004240042400424004240042
16020440041310100000322524010480100160004100160020500144013200400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511700016004003880000080000801004004240042400424004240042
1602044004131000000012962524010480100160004100160020500144013200400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511700016004003880000080000801004004240042400424004240042
16020440041311001198016782524010480100160004100160020500144013200400224004140041199776199921601202001600322001600324004140041218020110099100801001000030111511700016004003880000080000801004004240042400424004240042
16020440041310000000742524010480100160004100160020500144013200400224004140041199776199921601202001600322001600324004140041118020110099100801001000100111511700016004003880188080000801004028640124400424004240042
1602044012231300002680322524010480100160004100160020500144013200400224004140041199776199921601202001600322001600324004140041118020110099100801001000132111511700016004003880000080000801004004240042400424004240042
16020440041310000000322524010480100160004100160020500144013200400224004140041199776199921601202001600322001600324004140041118020110099100801001000000131511700016004003880000080000801004004240042400424004240042
160204400413100001200742524010480100160004100160020500144013200400224004140041199776199921601202001600322001600324004140041118020110099100801001000400111511700016004003880000080000801004004240042400424004240042
16020440041311000000322524010480100160004100160020500144013200400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511700016004003880000080000801004004240042400424004240042
160204400413110000006972524010480100160196100160020500144013210400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511700016004003880000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03191e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8acc2cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16002440042310072422524001080010160000101600005014400004002204004140041199963200211600102016000020160000400414004111800211091080010100000502021622400388000080000800104004240042400424004240042
1600244004132206702524001080010160000101600005014400004002204004140041199963200211600102016000020160000400414004111800211091080010100001502021622400388000080000800104004240042400424004240042
1600244004131006422524001080010160000101600005014400004002204004140041199963200211600102016000020160000400414004111800211091080010100000502021622400388000080000800104004240042400424004240042
1600244004131000422524001080010160000101600005014400004002204004140041199963200211600102016000020160000400414004111800211091080010100000502021632400388000080000800104004240042400424004240042
16002440041311005172524001080010160000101600005014400004002204004140041199963200211600102016000020160000400414004111800211091080010100000502031623400388000080000800104004240042400424004240042
1600244004131106422524001080010160000101600005014400004002204004140041199963200211600102016000020160000400414004111800211091080010100000502051633400388000080000800104004240042400424004240042
16002440041310001232524001080010160000101600005014400004002204004140041199963200211600102016000020160000400414004111800211091080010100000502031633400388000080000800104004240042400424004240042
1600244004131100422524001080010160000101600005014400004002204004140041199963200211600102016000020160000400414004111800211091080010100000502021623400388000080000800104004240042400424004240042
1600244004131000422524001080010160000101600005014417904002204004140041199963200211600102016000020160000400414004111800211091080010100000502031622400388000080000800104004240042400424004240042
16002440041310027702524001080010160000101600005014400004002204004140041199963200211600102016000020160000400414004111800211091080010100000502021632400388000080000800104004240042400424004240042