Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTMU (scalar, D to X)

Test 1: uops

Code:

  fcvtmu x0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)03191e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
20045414004325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414094325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045415004325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000052254154124832742000200020005415411110011000037311611538100010001000542542542542542
20045414004325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414008525300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtmu x0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030809181e3f4f5051inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8a9acc2c5cfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300389740200130059119417025401001010020000100001002000010000500621497914801034130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000131013164312952510000100001000010100130039130039130039130039130039
302041300389740000130023119417025401001010020000100001002000010000500621497914801034130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000131013163312954910000100001000010100130039130039130039130039130039
302041300389740000130023119417025401001010020000100001002000010000500621497914801034130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000131013163312952510000100001000010100130039130039130039130039130039
302041300389740000130023119417025401001010020000100001002000010000500621497914801034130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000020000131013162312952910000100001000010100130041130039130039130201130039
302041300409740000130023119417025401001010020000100001002000010000500621497914801034130015013003813003812547631262483010020010000200002001000020000130038130039112020110099100101001000010001000912300131013163312952610000100001000010100130039130039130039130039130039
302041300409740000130023119420025401001010020000100001002000010000500621497914801370130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000010000138413164312952510000100001000010100130039130039130039130039130039
302041300389740000130023119417025401001010420000100001002000010000500621497914801034130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000131014163312952510000100001000010100130039130039130039130039130039
302041300389740000130023119417025401001010020000100001002000010000500621497914801034130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000131013163312952510000100001000010100130039130040130039130039130039
3020413007197400030130102119417025401001010020000100001002000010000500621497914801034130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000131013163312952510000100001000010100130039130039130039130039130039
302041300389740000130023119417025401001010020000100001002000010000500621497914801034130013013003813003812547631262463010020010000200002001000020000130038130041112020110099100101001000010021000042320131014163312953310000100001000010100130039130039130049130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8a9acc2branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ecld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038100800000013002311941725400101001020000100001020000100005062149791480002511300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000127011611129546100000100001000010010130039130039130039130075130039
30024130038100800000013002311941725400101001020000100001020000100005062156511480735611300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000127011611129525100000100001000010010130039130039130039130039130039
300241300381008000000130023119417254001010010200001000010201211000050621497914804334113001301300391300441254983126268300102010000200002010000200001300381300381120021109101001010000100100004021000127011611129525100000100001000010010130039130039130039130039130039
30024130038100800000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000127011612129525100000100001000010010130308130070130091130042130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002511300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000127011611129525100000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020115100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000006000127021611129525100000100001000010010130041130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000127011611129525100000100001000010010130039130075130039130039130076
3002413003897400000013002311941725400101001020000100001020000100005062149791480002511300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000127011611129525100000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000018000127011611129525100000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002511300130130038130077125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000127021611129525100000100001000010010130039130039130039130039130045

Test 3: throughput

Count: 8

Code:

  fcvtmu x0, d8
  fcvtmu x1, d8
  fcvtmu x2, d8
  fcvtmu x3, d8
  fcvtmu x4, d8
  fcvtmu x5, d8
  fcvtmu x6, d8
  fcvtmu x7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8acc5branch mispredict (cb)cdcfd5d6e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1602044006229907625240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117116400388000080000801004004240042400424004240042
160204400413000141252401048010016000410016002050014401320400224014040041199773619992160120200160032200160032400414004111802011009910080100100001115117016400388000080000801004004240042400424004240042
16020440041300012025240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117016400388000080000801004004240042400424004240042
16020440041300018725240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117016400388000080000801004004240042400424004240042
16020440041300020425240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117016400388000080000801004004240042400424004240042
16020440041300011825240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117016400388000080000801004004240042400424004240042
160204400413000141925240104801001600041001600205001440132040022400414012519977619992160324200160032200160032400414012811802011009910080100100001115117016400388000080000801004004240042400424004240042
1602044004129907625240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117016400388000080000801004004240042401294004240042
16020440041299067025240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117016400388000080000801004004240042400424004240042
1602044004130007625240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100301115117016400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03181e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8acc5branch mispredict (cb)cdcficache miss (d3)itlb miss (d4)d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244004230000422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010101000050200028161628400388000080000800104004240042400424004240042
160024400412990015425240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101013900050200027162726400388000080000800104004240042400424004240042
16002440041300004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101013000050200026162714400388000080000800104004240042400424004240042
160024400412990070725240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101048000050200027161427400388000080000800104004240042400424004240042
1600244004129900422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010101900050200026162727400388000080000800104004240042400424004240042
1600244004130000422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010101000050200026162827400388000080000800104004240042400424012840042
160024400413110012625240010800101607821016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101061000050200016162822400388000080000800104004240042400424004240042
16002440041299004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101051000050200027162727400388000080000800104004240042400424004240042
16002440041300004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101057000050200013162822400388000080000800104004240042400424004240042
16002440041300004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101047600050200028162727400388000080000800104004240042400424004340042